Norikazu Hashimoto

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 /spl mu/m to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFTs for load devices. The effect of the Si/sub 3/N/sub 4/ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6/spl times/10/sup 6/ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns. >

Novel high density, stacked capacitor MOS RAM

A novel one transistor type MOS RAM cell is successfully developed and achieves a higher degree of integration than realized to date with conventional RAMs. This cell provides remarkable area reduction and/or an increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This new cell has a triple level poly-Si structure of poly-Si word lines and Al bit lines. The stacked capacitor is composed of a poly-Si - Si3N4- poly-Si structure. A 256 bit STC MOS RAM is fabricated with 3 µm technology and operates successfully. The STC RAM cell area, 52.5 µm2, is remarkably smaller than the cell area of conventional RAMs with double level poly-Si gate structure, 160 µm2.

A polysilicon transistor technology for large capacity SRAMs

A polysilicon PMOS cell technology is discussed. Bottom-gated polysilicon PMOS transistors are stacked over NMOS transistors, and a 17 mu m/sup 2/ cell size is realized with a 0.6 mu m design rule. In order to achieve high-performance polysilicon PMOS, both gate oxide and channel polysilicon thicknesses of the PMOS are reduced to 40 nm. A 0.4 mu m length gate-to-drain offset structure is adopted. Moreover, two novel approaches to O/sub 2/ plasma treatment prior to metal H/sub 2/-N/sub 2/ anneal and oxidation of channel polysilicon have been found to be effective for achieving excellent polysilicon PMOS characteristics. As a result, polysilicon PMOS which has a 25 fA off-current (V/sub d/=-5 V, V/sub g/=0 V) and a 0.1 nA on-current (V/sub d/=-5 V, V/sub g/=-2 V) has been realized.<<ETX>>

A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity

A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers retention voltage to less than 0.5 V and the soft error rate (SER) under high-speed operation by about an order of magnitude. A 5-fF cross-coupled capacitor improves the retention mode SER by more than an order of magnitude and low standby power is attained with a 0.1-pA OFF current of the poly-Si PMOS. The performance has been evaluated using a 4-kbit SRAM. The cell area has been reduced to 25.38 mu m/sup 2/ using half-micron CMOS technology.<<ETX>>

An n-well CMOS dynamic RAM

A new n-well CMOS dynamic RAM is proposed. Experimental results with a 4K RAM, fabricated with advanced 2-/spl mu/m lithography, are presented. For the design of RAMs greater than 256K, two major problems need to be solved: the increase in substrate current, and alpha-particle-induced soft errors. The new n-well CMOS RAM technology provides a solution to these problems. Use of PMOS transistors as load elements in peripheral circuits of the n-well CMOS RAM reduces the substrate current by at least two orders of magnitude. In addition, the potential barrier between the n-type well and the p-type substrate rejects holes generated in the substrate, resulting in the reduction of soft error rates.

A high-performance N-channel MOS-LSI using depletion-type load elements

A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved. >

A 5-V Only 16-kbit Stacked-Capacitor MOS RAM

A novel one-transistor-type MOS RAM is discussed. This memory cell gives a remarkable area reduction and/or increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor, bit lines, or field oxides. It is callled a stacked-capacitor (STC) RAM. This STC memory has a three-level poly-Si structure. The stacked capacitor has poly-Si-Si/sub 3/N/sub 4/-poly-Si (or Al) structure. A 16-kbit STC RAM has been fabricated with 3-/spl mu/m technology and operated successfully. Memory performance is strikingly improved by using STC cells.

Ellipsometric study of annealing processes of phosphorus‐ion‐implanted layers of Si

The annealing processes of high‐dose P+‐ion‐implanted Si are studied by ellipsometry. The change in ellipsometric angle (Δ, ψ) during isothermal annealing is measured and compared with that of values calculated using a simple epitaxial regrowth model based on the distribution of the optical constants. The discrepancy between the experimental and the calculated change in angle shows imperfectness of annealing in the 500–550 °C temperature range.

Measurements of Compositional Change in Semi-Insulating GaAs Single Crystals by Precise Lattice Parameter Measurements

Precise lattice parameter measurements have been made for semi-insulating GaAs, and it is found that the lattice parameters vary greatly (order of 10-4 A) among GaAs wafers and in a wafer. This variation of lattice parameter is closely related to the threshold voltage of the FETs, which are made by direct ion implantation on the crystal. The change of the lattice constant is probably caused by the interstitial As atoms, and a slight change of crystal growth condition may cause its variation in the wafer. Variation of the As concentration affects the threshold voltage of MESFETs when they are made by direct ion implantation.