Masaharu Yamaji

A Simple Low Cost Monolithic Transformer for High-Voltage Gate Driver Applications

A simple low cost monolithic 3D through-silicon-via coreless transformer is designed and fabricated for high-voltage gate driver applications. The transformer comprises the primary coil embedded in the bottom layer of a Si substrate and the secondary coil built on the front-side of the substrate. Compared with conventional transformers with both coils built on the front-side or at the backside, the proposed structure has the advantages of area-saving and cost-effectiveness. A coreless transformer with primary, secondary, and mutual inductances of 260, 280, and 112 nH, respectively, is fabricated in a small area of 2 mm2. It achieves both high galvanic isolation and satisfactory voltage gain (0.41 from 4 to 45 MHz).

A new level up shifter for HVICs with high noise tolerance

In this paper, a new level up shifter with high dV/dt and negative transient voltage noise immunities is presented. The proposed level up shifter achieves high noise immunity without an increase in the delay time of high-voltage ICs (HVICs). A fabricated 1200 V-class HVIC adopting the proposed level up shifter on a p-type substrate indicates a stable operation under the conditions of dV/dt noise over 50 kV/μs and negative transient voltage noise of -150 V. And we have confirmed the good performances of a 3-phase inverter driven by the fabricated HVIC.

A novel 3D TSV transformer technology for digital isolator gate driver applications

In this paper, a novel 3D TSV (Through-Silicon-Via) transformer technology for power system-on-chip applications is proposed and demonstrated experimentally. The transformer used in the power system features a galvanic isolation of > 4 kV and a voltage gain of > -3 dB from 10 MHz to 100 MHz. It can be embedded in the bottom layer of a silicon substrate and sandwiched between system circuitries for ultimate area efficiency and the smallest possible form factor compared with other conventional on-silicon approaches. A digital isolator gate driver built using this transformer technology is achieved, and successful signal transfer is clearly illustrated.

High side n-channel and bidirectional Trench Lateral Power MOSFETs on one chip for DCDC converter ICs

Trench lateral power MOSFETs (TLPMs) are suitable for one chip power ICs due to its low specific on- resistance and ease of fabrication with CDMOS devices. In our smart power IC process we integrated both the high side n- channel and bidirectional TLPMs in one chip. In addition, better device characteristics of both devices were obtained with the process integration technology. The high side MOSFET shows 20 mOmegamm2 specific on-resistance with 25 V breakdown voltage and excellent reliability. The bidirectional MOSFET shows 7.0 mOmegamm2 specific on-resistance, which represents 67% of the current mass production value, with a breakdown voltage of 25 V.

1200V-Class HVIC technology with a divided high-side well structure for high-functionality and downsizing of circuits

A novel high-side well structure for a 1200V-class HVIC on a p-type substrate has been developed. The high-side well structure, consists of divided well regions with different voltage, makes it possible to integrate multiple circuits driven by different supply voltages on the high-side region in the HVIC. With implementing the developed structure, IGBT protection circuits on the high-side can be allocated 17% smaller area, and a 1200V-class HVICs with high functionality and high noise tolerance has been developed.

700V PIC technology based on 0.35µm design for AC-DC power units

We have established the 700V-class PIC technology based on 0.35μm design to provide power management ICs with higher performances and lower chip cost for the first time. And a 700V PWM-IC based on 0.35μm design, whose chip size can be reduced to 50% that of the IC based on 1.0μm design, is realized. This paper will report our developed 700V PIC technology with a PWM-IC product designed by this technology.

A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink

A novel 600 V high-voltage IC (HVIC) featuring a high noise tolerance is proposed. The purpose of the proposed HVIC is to achieve the high noise tolerance without an increase of the fabrication cost. The basic device concept is to arrange a P- separation layer around the high-side control part, which is called a new self-shielding structure, to reduce a hole current injection under the condition of negative transient voltage noise. By applying the new self-shielding structure in the HVIC, more than 3× higher noise tolerance (-95 V/1 μs) and 20% die shrink can be obtained compared with a conventional HVIC, without additional fabrication process. This means the noise tolerance of the fabricated HVIC with proposed structure is high enough to be applied to over 600 V/50-A class power conversion applications. In this paper, the new self-shielding concept of the proposed 600 V-class HVIC is presented with the simulation and experimental results.

A new downsized HVIC with high ESD tolerance

To achieve a downsized high voltage integrated circuit (HVIC) with high electrostatic discharge (ESD) tolerance, we have proposed the improved self-shielding technique in which a high voltage junction termination (HVJT) diode works as a protection diode of high voltage Neh MOSFETs. This new technique is more effective not only in improving ESD tolerance but also in downsizing.

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

A new 800 V-class lateral high-voltage n-channel MOS (HVNMOS) structure with a markedly reduced parasitic capacitance (Coss) has been developed for integration in a high-voltage gate driver IC. In our new HVNMOS, a 40% Coss reduction from that of a conventional HVNMOS can be achieved by using two n-type drift regions divided by a p-type diffusion layer. We have confirmed that a 12% shorter I/O propagation delay time can be achieved by using the new HVNMOS of the high-voltage IC (HVIC) test chip. In this paper, the design concept of the developed HVNMOS is presented with the simulation and experimental results.