Hitoshi Sumida

A Simple Low Cost Monolithic Transformer for High-Voltage Gate Driver Applications

A simple low cost monolithic 3D through-silicon-via coreless transformer is designed and fabricated for high-voltage gate driver applications. The transformer comprises the primary coil embedded in the bottom layer of a Si substrate and the secondary coil built on the front-side of the substrate. Compared with conventional transformers with both coils built on the front-side or at the backside, the proposed structure has the advantages of area-saving and cost-effectiveness. A coreless transformer with primary, secondary, and mutual inductances of 260, 280, and 112 nH, respectively, is fabricated in a small area of 2 mm2. It achieves both high galvanic isolation and satisfactory voltage gain (0.41 from 4 to 45 MHz).

A New Trench Power MOSFET With an Inverted L-Shaped Source Region

A new trench power MOSFET with an inverted L-shaped source region is proposed and experimentally demonstrated. The fabricated new device has a breakdown voltage of 54 V. The avalanche energy absorption of the new device at unclamped inductive switching is 2.1 times that of the fabricated conventional trench power MOSFET. This is due to the minimized n+-source/p-body junction in the structure. Moreover, the specific on-resistance of the new device is reduced by 30% due to the smaller pitch. The new device is very promising for automotive electric power steering applications.

A novel 3D TSV transformer technology for digital isolator gate driver applications

In this paper, a novel 3D TSV (Through-Silicon-Via) transformer technology for power system-on-chip applications is proposed and demonstrated experimentally. The transformer used in the power system features a galvanic isolation of > 4 kV and a voltage gain of > -3 dB from 10 MHz to 100 MHz. It can be embedded in the bottom layer of a silicon substrate and sandwiched between system circuitries for ultimate area efficiency and the smallest possible form factor compared with other conventional on-silicon approaches. A digital isolator gate driver built using this transformer technology is achieved, and successful signal transfer is clearly illustrated.

UIS Analysis and Characterization of the Inverted L-Shaped Source Trench Power MOSFET

In this paper, the unclamped inductive switching (UIS) behavior of an inverted L-shaped source trench power MOSFET is numerically analyzed and experimentally characterized. The measured avalanche energy absorption at UIS of the new trench power MOSFET is 2.1 times that of the conventional trench power MOSFET. This is explained by numerical simulation, which shows that the voltage drop across the emitter/base junction in the parasitic bipolar junction transistor of the new structure is smaller than that of the conventional structure. The influence of structural and device size variation of the new trench power MOSFET on UIS performance is also investigated. Results show that the avalanche current density at UIS is a strong function of the p+-region width and the device size. Furthermore, the effect becomes very significant as the device size becomes very small.

The characteristics of the lateral IGBT on the thin SOI film when the collector voltage of the IGBT is applied to the substrate

The characteristics of the lateral IGBT on an SOI film when the collector voltage of the IGBT is applied to the substrate are investigated for its application to a high side switch. The measurements of the blocking capability and the dynamic latch-up current during the turn-off transient under an inductive load are carried out with varying thicknesses of the SOI film. A 260 V IGBT can be fabricated on a 5 /spl mu/m thick SOI film without the special device structure. The dynamic latch-up current is improved by reducing the SOI film thickness. This paper shows that applying the collector voltage of the IGBT to the substrate makes it possible to improve the characteristics of the IGBT on a thin SOI film. >

A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink

A novel 600 V high-voltage IC (HVIC) featuring a high noise tolerance is proposed. The purpose of the proposed HVIC is to achieve the high noise tolerance without an increase of the fabrication cost. The basic device concept is to arrange a P- separation layer around the high-side control part, which is called a new self-shielding structure, to reduce a hole current injection under the condition of negative transient voltage noise. By applying the new self-shielding structure in the HVIC, more than 3× higher noise tolerance (-95 V/1 μs) and 20% die shrink can be obtained compared with a conventional HVIC, without additional fabrication process. This means the noise tolerance of the fabricated HVIC with proposed structure is high enough to be applied to over 600 V/50-A class power conversion applications. In this paper, the new self-shielding concept of the proposed 600 V-class HVIC is presented with the simulation and experimental results.

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

A new 800 V-class lateral high-voltage n-channel MOS (HVNMOS) structure with a markedly reduced parasitic capacitance (Coss) has been developed for integration in a high-voltage gate driver IC. In our new HVNMOS, a 40% Coss reduction from that of a conventional HVNMOS can be achieved by using two n-type drift regions divided by a p-type diffusion layer. We have confirmed that a 12% shorter I/O propagation delay time can be achieved by using the new HVNMOS of the high-voltage IC (HVIC) test chip. In this paper, the design concept of the developed HVNMOS is presented with the simulation and experimental results.