Rihito Kuroda

A linear response single exposure CMOS image sensor with 0.5e − readout noise and 76ke − full well capacity

A linear response single exposure CMOS image sensor approaching to the photon countable sensitivity and a high full well capacity (FWC) is developed using lateral overflow integration capacitor (LOFIC) architecture with dual gain column amplifiers, small floating diffusion (FD) capacitance (C_FD) and low noise in-pixel source follower (SF) signal readout technologies. The fabricated 5.5 μm pitch 360^H×1680^V pixel prototype image sensor exhibited 240 μV/e^- conversion gain (CG) with 76 ke^- FWC resulting in 0.5 e^-_rms readout noise and 104 dB dynamic range under room temperature operation.

Analyzing correlation between multiple traps in RTN characteristics

The correlation between multiple traps in Random Telegraph Noise (RTN) were evaluated by using Time-Lag-Plot (TLP). The correlations between multiple traps were evaluated by transition paths on the TLP and there are two types of RTN. In the 1st case, multiple traps are independent from each other and in the second case the multiple traps have the correlation. We proposed the models for three states RTN to understanding the mechanism of them. These methods help us to understand the RTN mechanism and the correlation between multiple traps.

Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate–source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

Random telegraph noise measurement and analysis based on arrayed test circuit toward high S/N CMOS image sensors

Using the developed array test circuit, both static and temporal electrical characteristics of over million transistors/shot were measured with the accuracy of 60 μVrms to analyze and reduce random telegraph noise (RTN) toward high S/N CMOS image sensors. Statistical evaluation results of RTN parameters such as time constants and amplitude and their behaviors toward transistor device structures and operation conditions are summarized. Application to high S/N CMOS image sensor is also described.

A novel analysis of oxide breakdown based on dynamic observation using ultra-high speed video capturing up to 10,000,000 frames per second

Dynamic visualization results of 100 nm-thick oxide breakdown are demonstrated in this work realized by the ultra-high speed video capturing with a frame rate of up to 10M frame-per-second. The correlation of the time-dependent-dielectric-breakdown failure mode and light emission mode are confirmed.

Analysis of pixel gain and linearity of CMOS image sensor using floating capacitor load readout operation

In this paper, we demonstrate that the floating capacitor load readout operation has higher readout gain and wider linearity range than conventional pixel readout operation, and report the reason. The pixel signal readout gain is determined by the transconductance, the backgate transconductance and the output resistance of the in-pixel driver transistor and the load resistance. In floating capacitor load readout operation, since there is no current source and the load is the sample/hold capacitor only, the load resistance approaches infinity. Therefore readout gain is larger than that of conventional readout operation. And in floating capacitor load readout operation, there is no current source and the amount of voltage drop is smaller than that of conventional readout operation. Therefore the linearity range is enlarged for both high and low voltage limits in comparison to the conventional readout operation. The effect of linearity range enlargement becomes more advantageous when decreasing the power supply voltage for the lower power consumption. To confirm these effects, we fabricated a prototype chip using 0.18um 1-Poly 3-Metal CMOS process technology with pinned PD. As a result, we confirmed that floating capacitor load readout operation increases both readout gain and linearity range.

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

In this work, the origin of the leakage current of a highly area-efficient silicon-on-insulator (SOI) monolithic isolator using a spiral trench isolation structure is clarified by experimental and simulation analyses and its reduction method is proposed. It was found that parasitic MOSFET inversion and accumulation channels formed at the SOI and buried oxide (BOX) interface are the origins of leakage current. To reduce the leakage current, adequate SOI spiral length and width and BOX layer thickness are proposed for various voltage usages and show the possibility of 4 kV voltage tolerance and 500 MΩ isolation resistivity.

An ultraviolet radiation sensor using differential spectral response of silicon photodiodes

An ultraviolet (UV) sensor is demonstrated with high sensitivity in the UV waveband and low sensitivity in the visible (VIS) and near-infrared (NIR) wavebands, utilizing only bulk silicon technology. The developed sensor utilizes the differential spectral response of photodiodes (PDs) with a high UV sensitivity (PD1) and a low UV sensitivity (PD2), for UV signal extraction under a VIS and NIR light background. To suppress the effects of incident light spatial strength distribution over the sensor, PD1 and PD2 were arranged in a checkered pattern of 8×6 PDs. High Signal to Noise Ratio (SNR) for UV signal extraction was achieved by a developed prototype UV sensor circuit consisted of charge amplifiers connected to PDs and a differential amplifier. The fabricated PD chip has a total area of 1.2 mm2, PD1 and PD2 showed a sensitivity of 0.16 A/W and 0.02 A/W at 310 nm, respectively. The spectral response of the UV sensor was measured and the UV waveband selective sensitivity was successfully obtained.

UV/VIS/NIR imaging technologies: challenges and opportunities

Challenges and opportunities of ultraviolet (UV), visible (VIS) and near-infrared (NIR) light imaging technologies are overviewed in this paper. For light detectors and image sensors for UV/VIS/NIR imaging, it is required that they have high sensitivity for wide spectral light waveband or targeted narrow waveband as well as the high stability of light sensitivity toward UV light based on cost effective technology. Wide spectral response, high sensitivity and high stability advanced Si photodiode (PD) pn junction formation technology based on the flattened Si surface and high transmittance on-chip optical filter formation technology were developed. A linear photodiode array (PDA), wide dynamic range and ultrahigh speed CMOS image sensors employing the developed technology were fabricated and their advanced performances are described in this paper.

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

We analyzed the shared voltages of multiple trench gaps on a silicon-on-insulator (SOI) substrate and showed the conditions for improving the breakdown voltage surrounded by these isolated structures. We introduced a unified impedance model instead of the capacitive model of trench gaps and determined the effective conditions for improving the breakdown voltage. The first condition is to reduce the impedance of trench gaps. In this case, the leak current gives a low limit of trench gap resistance. The second condition is to increase the substrate resistance. As silicon substrate resistance is not very high, this condition is not useful for the silicon substrate, but for other materials such as ceramics. We confirmed the effectiveness of these conditions from the simulation and experimental results of a fabricated chip.