Masahiro Miyairi

Development of practical flare correction tool for full chip in EUV lithography

A practical flare-aware optical proximity correction (OPC) tool for full-chip level has been developed for upcoming extreme ultraviolet lithography (EUVL). The conventional flare-aware OPC method for EUVL is unsuitable for practical use because it requires enormous time for lithography simulation to compensate for the long-range flare effect. By separating the lumped flare-aware OPC step into (1) the OPC step and (2) the flare correction step, the runtime required for lithography simulation is reduced to 1% by applying the same OPC for the identical pattern at different positions in step 1. And we found that there is a linear relation between amount of flare and correction bias for each pattern variation. Using this relation, a fast rule-based correction method can be adopted in step 2 without deterioration of correction accuracy for any pattern variation. Our new correction tool reduces the run-time to 1/70, which means it is the same as in the case of optical lithography for full-chip level, and also satisfies the target OPC residual of ±1nm. Consequently, it has been demonstrated that our new correction is practical and promising for the full-chip in EUVL in terms of run-time and correction accuracy.

A full chip MB-SRAF placement using the SRAF guidance map

A fast model-based technique for SRAF placements is proposed in this paper. This technique first constructed an image pixel map with values presenting the sensitivity of improving process window on the desired pattern. The sensitivity value was derived based on contrast improvement with a defocus model. Then high value pixels were selected and constructed to form SRAF with MRC regulations. This technique does not require iterations to produce SRAF and achieves very fast runtime with simple mask shapes, thus can be used in full-chip productions. We called this technique the SRAF guidance map, SGM

Hotspot detection using image pattern recognition based on higher-order local auto-correlation

Below 40nm design node, systematic variation due to lithography must be taken into consideration during the early stage of design. So far, litho-aware design using lithography simulation models has been widely applied to assure that designs are printed on silicon without any error. However, the lithography simulation approach is very time consuming, and under time-to-market pressure, repetitive redesign by this approach may result in the missing of the market window. This paper proposes a fast hotspot detection support method by flexible and intelligent vision system image pattern recognition based on Higher-Order Local Autocorrelation. Our method learns the geometrical properties of the given design data without any defects as normal patterns, and automatically detects the design patterns with hotspots from the test data as abnormal patterns. The Higher-Order Local Autocorrelation method can extract features from the graphic image of design pattern, and computational cost of the extraction is constant regardless of the number of design pattern polygons. This approach can reduce turnaround time (TAT) dramatically only on 1CPU, compared with the conventional simulation-based approach, and by distributed processing, this has proven to deliver linear scalability with each additional CPU.

Lithography compliance check considering neighboring cell structures for robust cell design

Lithography compliance check (LCC), which is verification of layouts using lithography simulation, is an essential step under the current low k1 lithography condition. In general, LCC starts from primitive cell block level and checks bigger block level in the final stage. However, hotspots may be found by chip level LCC although LCC does not find any hotspots in a primitive cell block check, because conventional LCC for primitive cell blocks cannot consider the influence of the optical proximity effect from neighboring cell structures at the chip level. This paper proposes a new verification method in order to resolve this issue. It consists of three steps. The first step is the same as the conventional method; run LCC and judge if there are hotspots, which need to be fixed. The second step is judge if there are warmspots, which represent the pattern structures with borderline litho margin, and if warmspots are found, add a pattern that makes process margin worst. The third step is to fix the hotspots changing from warmspots by adding the worst pattern. Based on this method, primitive cell block LCC can guarantee that there are no hotspots at the chip level without chip level LCC. We discuss the detail of process flow of this verification method and validate the effect of this method.