Taiga Uno

Hierarchical Processing of Levenson-Type Phase Shifter Generation

The hierarchical processing of Levenson-type phase shifter generation has been developed. It is integrated with a computer aided design (CAD) system, which makes modification of conflict spots easy for designers. In order to keep CAD data compressed during phase assignment, phase information is stored as a combination of two properties, phase and group reversal. Phase assignment is generally executed cell-by-cell from the bottom up. In each cell, the region processed is kept to a minimum in order to achieve efficient processing. The intrinsic problem of bottom-up hierarchical processing is the merge problem in which patterns to be merged at the cell boundary have different phases, and it is treated with retry processing. The hierarchical phase assignment was applied to 4M-bit memory with a core circuit and the effectiveness of the hierarchical processing was demonstrated. The processed data were compressed to about 1/20, and processing time was reduced by at least 1/2 of those by flat processing.

EUV flare correction for the half-pitch 22nm node

Extreme ultraviolet lithography (EUVL) is one of the most promising candidates for the next-generation lithography. For the adoption of EUVL, however, there are some technological issues to be solved. One of the critical issues is flare which is an undesirable scattered light that reduces the aerial image contrast leading to a reduction in the process window such as exposure latitude. Therefore, new methods to compensate for the anticipated flare effect have to be devised. At Selete, flare correction based on a flare point-spread function (PSF) is investigated. We succeeded in achieving a CD control of within a few nm over various pattern densities for the half-pitch (HP) 32-nm node. However, our estimation shows that the previous flare correction scheme could not meet the accuracy criteria of flare computation for HP 22-nm node. Therefore, we have modified the flare correction flow to implement a variable gridding for pattern-density calculation. The variable gridding based on the shape of a PSF enables highly accurate flare calculation within a reasonable runtime. Furthermore, we will use model-based OPC for HP 22-nm node, whereas we normally use rule-based OPC for HP 32- nm node. This is because the lithography process is reaching the low k1 regime. In this work, we investigate the feasibility of model-based OPC incorporating flare correction.

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

Solution for 100 nm: EBM-4000

Optical lithography will be extended down to 65nm to 50 nm. However, a mask with high accurate CD uniformity and resolution enhancement technology (RET) such as optical proximity effect correction (OPC) and phase shifting mask (PSM) are required to achieve resolution by exposure wave length. The mask technology is the key of the optical lithography extension. We developed the electron beam mask writer EBM-3000 for 180-150nm design rule 1), 2), and EBM-3500 for 150-130nm design rule 3), to achieve high accuracy CD uniformity mask and small OPC pattern writing. They were variable shaped electron beam mask writing system with continuous moving stage, at 50kV acceleration voltage, and had the functions of multi-pass field shift writing, real-time proximity effect correction, grid matching correction, and automatic adjustment for election optical column.The LSI road map calls for such small minimum feature size as that so close to optical resolution limitation where increasingly complex optical proximity corrections (OPC) as well as extremely good mask CD uniformity are required. What is making the challenge even more difficult is that writing time is exponentially increasing as the shot number is exploding to primarily cope with the complex and voluminous OPC and extremely good CD uniformity requirements. Thus the newly developed electron beam mask lithography system EBM-4000 is designed to overcome all these difficult problems associated with 100nm as well as 70nm node masks. In order to increase throughput, triangle/rectangle beam optical column, high current density/high resolution lens, and high speed DAC amplifiers have been developed. To achieve accurate CD uniformity, foggy electron correction/loading effect correction functions are developed.

Hierarchical optical proximity correction on contact hole layers

As the size of contact holes shrinks below 0.2 /spl mu/m, optical proximity correction (OPC) on contact hole layers becomes essential. When correcting contact holes, 1-dimensional correction is not applicable, and 2-dimensional correction is required, which needs much more intensive computation. To reduce computation, it is very effective to take advantage of the hierarchy of the input data. In order to further accelerate the OPC calculation, we adopted pattern matching into the OPC system, which can extract the hierarchy implicit in the layout data.

High accurate process proximity correction based on empirical model for 0.18 /spl mu/m generation and beyond

A pattern correction engine with high accuracy was developed for a full chip level process proximity correction (PPC) system. The performance was demonstrated by core circuit patterns with 0.18/spl mu/m-ground rule in a test site of 1 giga-bit dynamic random access memory (DRAM). There are two main important points for high accurate PPC. One is the prediction accuracy of the pattern feature after etching. The conventional single gaussian model is not sufficient but the empirical model based on multiple gaussian functions is necessary for predicting the feature after etching. Another is the fitting accuracy of the empirical model to the experimental data without process fluctuation and measurement noise. This paper focus on the empirical model fitting and the prediction accuracy.

Process liability evaluation for beyond 22nm node using EUVL

Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22- nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer process for device manufacture at the 22-nm node and beyond.

Process liability evaluation for EUVL

This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.

Flare compensation for EUVL

At Selete, correction for flare based on a flare point-spread function (PSFF) is investigated. We divide a layout into a grid and calculate pattern density for each grid square, obtaining a density array as an approximation to the layout aerial image. Then, the density array is convolved with the PSFF to create an array of flare values. Using this flare-value array, we resize the layout. In the above correction flow, size of a grid square of density array and a selection of an approximate function of the PSFF have a great influence on the accuracy of flare value computation. In this study, correction for flare was applied to the fabrication of several test masks using the real PSFF obtained from a full-field step-and-scan exposure tool called EUV1. We report on the optimization of size of grid square, on a suitable approximation model of PSFF, and on feedbacks from exposure experiments.

Development of practical flare correction tool for full chip in EUV lithography

A practical flare-aware optical proximity correction (OPC) tool for full-chip level has been developed for upcoming extreme ultraviolet lithography (EUVL). The conventional flare-aware OPC method for EUVL is unsuitable for practical use because it requires enormous time for lithography simulation to compensate for the long-range flare effect. By separating the lumped flare-aware OPC step into (1) the OPC step and (2) the flare correction step, the runtime required for lithography simulation is reduced to 1% by applying the same OPC for the identical pattern at different positions in step 1. And we found that there is a linear relation between amount of flare and correction bias for each pattern variation. Using this relation, a fast rule-based correction method can be adopted in step 2 without deterioration of correction accuracy for any pattern variation. Our new correction tool reduces the run-time to 1/70, which means it is the same as in the case of optical lithography for full-chip level, and also satisfies the target OPC residual of ±1nm. Consequently, it has been demonstrated that our new correction is practical and promising for the full-chip in EUVL in terms of run-time and correction accuracy.