Shimon Maeda

Novel error mode analysis method for graphoepitaxial directed self-assembly lithography based on the dissipative particle dynamics method

Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full advantage of DSAL requires diminishing not only systematic error modes but also random error modes by carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only systematic errors but also random errors qualitatively by simulations.

Optimization of directed self-assembly hole shrink process with simplified model

Abstract. Application of the directed self-assembly of block copolymer to the hole shrink process has gained large attention because of the low cost and high potential for sublithographic patterning. In this study, we have employed a simplified model, called the Ohta-Kawasaki model to find the optimal process conditions, which minimize the morphological defects of the diblock copolymer, PS-b-PMMA. The model parameters were calibrated with cross-sectional transmission electron microscopy images. Our simulation results revealed that it is difficult to eliminate the morphological defects (i.e., PS residual layer) by only varying the shape of the guide hole. It turned out that changing the affinity of the bottom surface of the guide hole from “PMMA attractive” to “neutral” is a more effective way to obtain a reasonably wide, defect-free process window. Note that our simulations are not only computationally inexpensive, but are also comparable to the other detailed models such as the self-consistent field theory; they may also be feasible for large-scale simulations such as the hotspot analysis over a large area.

Hotspot prevention and detection method using an image-recognition technique based on higher-order local autocorrelation

Abstract. Although a number of factors relating to lithography and material stacking have been investigated to realize hotspot-free wafer images, hotspots are often still found on wafers. For the 22-nm technology node and beyond, the detection and repair of hotspots with lithography simulation models is extremely time-consuming. Thus, hotspots represent a critical problem that not only causes delays to process development but also represents lost business opportunities. In order to solve the time-consumption problem of hotspots, this paper proposes a new method of hotspot prevention and detection using an image recognition technique based on higher-order local autocorrelation, which is adopted to extract geometrical features from a layout pattern. To prevent hotspots, our method can generate proper verification patterns to cover the pattern variations within a chip layout to optimize the lithography conditions. Moreover, our method can realize fast hotspot detection without lithography simulation models. Obtained experimental results for hotspot prevention indicated excellent performance in terms of the similarity between generated proposed patterns and the original chip layout patterns, both geometrically and optically. Moreover, the proposed hotspot detection method could achieve turn-around time reductions of >95% for just one CPU, compared to the conventional simulation-based approach, without accuracy losses.

Accurate model base verification scheme to eliminate hotspots and manage warmspots

Lithography compliance check (LCC), which is verification of layouts using lithography simulation, is an essential step under the current low k1 lithography condition. However a conventional LCC scheme does not consider process proximity effect (PPE) differences among several manufacturing tools, especially for exposure tools. In this paper two concepts are proposed. One is PPE monitoring and matching using warmspots. The warmspots are patterns that have small process window. They are sensitive to difference of illumination conditions and are basically 2-dimensional patterns. The other is LCC using multiple simulation models that represent each PPE on exposure tools. All layouts are verified by these models and the layouts are fixed if hotspots (catastrophic failure on wafer) are found. This verification step is repeated until all hotspots are eliminated from the layouts. Based on these concepts, robust cell layouts that have no hotspot under the several PPE conditions are created.

Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

Design intent application to tolerance-based manufacturing system

Continuous shrinkage of the design rule in large-scale integrated circuit devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension tolerance for each object, considering design intent in terms of electrical behavior, and assigning the tolerance for each process step. However, once the design data are converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process phase. Thus, uniform and redundant tolerance is used, and therefore, excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. Using a 40-nm node test chip, electrically critical spots, such as timing, cross-talk noise, electromigration, with small margins are extracted, assigned to the physical layout, and utilized in the manufacturing process. The flow is applicable for optical proximity effect correction (OPC) turnaround time reduction, optimization of OPC/lithography compliance check (LCC) specification, and failure-analysis acceleration. Consequently, a design-intent-aware manufacturing system is promising for realizing proper process specifications and computational cost reduction, in addition to yield enhancement.

Manufacturing system based on tolerance deduced from design intention

Scaling of integrated circuits over the past several ten years has been done successfully by improvement of photolithography equipment and resolution enhancement technique. The smaller the feature size is, the tighter controllability of critical dimension (CD) is required. Enormous efforts have been made to achieve device specifications. Especially in logic devices as system on chip, controllability of gate transistor CD is the one of the greatest concern for both designer and manufacturer since characteristics of device chip, speed and power, are largely depend on the gate CD. From the viewpoint of manufacturer all gate transistors on a chip have equivalent weight and tight CD controls are applied to them. Nevertheless, each transistor has a various weight and required controllability is definitely different from the viewpoint of chip designer. In this paper, we introduce the concepts of tolerance as representation of design intentions. An intention derived at chip designing stage is converted to a formula which is comprehensive and measurable at manufacturing1,2. Timing margin of each path, which is derived from timing analysis at chip design, can be converted to the most comprehensive formula as CD tolerance, for instance. Two major application of the tolerance deduced from design intention will be presented. The first one is reduction of OPC processing time and the second application of the tolerance is qualification at photo-mask and wafer processing. Comprehension of design intentions and interpretation of them to tolerance will be promising way for cost effective manufacturing.

Hotspot detection using image pattern recognition based on higher-order local auto-correlation

Below 40nm design node, systematic variation due to lithography must be taken into consideration during the early stage of design. So far, litho-aware design using lithography simulation models has been widely applied to assure that designs are printed on silicon without any error. However, the lithography simulation approach is very time consuming, and under time-to-market pressure, repetitive redesign by this approach may result in the missing of the market window. This paper proposes a fast hotspot detection support method by flexible and intelligent vision system image pattern recognition based on Higher-Order Local Autocorrelation. Our method learns the geometrical properties of the given design data without any defects as normal patterns, and automatically detects the design patterns with hotspots from the test data as abnormal patterns. The Higher-Order Local Autocorrelation method can extract features from the graphic image of design pattern, and computational cost of the extraction is constant regardless of the number of design pattern polygons. This approach can reduce turnaround time (TAT) dramatically only on 1CPU, compared with the conventional simulation-based approach, and by distributed processing, this has proven to deliver linear scalability with each additional CPU.

Design intention application to tolerance-based manufacturing system

Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step. Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully considered. Electrical behavior is carefully verified in both cell and chip design phases with respect to timing, IR drop, signal integrity, crosstalk, etc., using various electronic design automation (EDA) tools. However, once the design data is converted to layout data and signed off, most of the design intention is abandoned and unrecognized in the process phase. Thus, instead of essential tolerance according to layout-related design intention, uniform and redundant tolerance is used, and therefore excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intention has been discussed. In this paper, a test flow is developed and application to 45nm node test chip is examined.

RLT uniformity improvement utilizing multi-scale NIL process simulation

Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. To apply smaller pattern size device, layout dependent hotspots becomes a significant issue, so design for manufacturing (DFM) flow considering imprint process has to be prepared. In this paper, focused on fine resist spread, RLT (Residual Layer Thickness) uniformity improvement utilizing simulation is demonstrated and resist drop compliance check flow is proposed