Akira Tada

Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation

Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active bodybiasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of Vth variation on performance even at ultra low supply voltage less than 0.5 V.

Leakage power reduction for clock gating scheme on PD-SOI

This paper presents a technique for reducing leakage power of the circuits employing a clock gating scheme on Partially Depleted Silicon On Insulator (PD-SOI). To reduce leakage power while a local clock is disabled, V/sub th/ of each transistor is dynamically controlled by body biasing corresponding to the mode of the local clock. Using PD-SOI is the key to control V/sub th/ within one clock cycle by forward biasing, where V/sub th/ without biasing is designed higher than usual to reduce leakage power. The SPICE simulation results have shown that the proposed technique reduces leakage power by 82% with small area penalty.

A novel power gating scheme with charge recycling

In MTCMOS, the circuit state should be preserved for state retentive sleep, and the virtual power/ground rails clamp (VRC) scheme is an effective method for this purpose. Our approach realizes the voltage clamp function without additional devices like diodes, by feeding the virtual ground voltage back into a sleep signal. There are also other effects; cutting off the leak current of the sleep buffer, and charge recycling of sleep signal node. We have achieved a 19.7% lower power consumption and a 5.4% cell area reduction.

Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation

In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (V DD ) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than V DD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.

Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM

This paper presents an SOI-SRAM design employing a bootstrap scheme for ultra low voltage operation. The active body-biasing control (ABC) with PD-SOI is a key idea to enhance the boosting effect owing to a strong capacitive coupling. Our ABC-bootstrap scheme enables boosting the word line (WL) voltage higher than the supply voltage in short transition time without dual power supply rails. Simulation results have shown improvement in both the access time and operation at ultra low supply voltage less than 0.5V

Improved write margin for 90nm SOI-7T-SRAM by look-ahead dynamic threshold voltage control

Instability of SRAM memory cells derived from aggressive technology scaling has recently been one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-lV, it unfortunately results in degradation of write margins. Then, we address a new memory cell adopting a look-ahead body-bias which dynamically controls the threshold voltage in order to assist the write operation. Simulation results have shown improvement in both the write margins and access time.

High performance CMOS circuit by using charge recycling active body-bias controlled SOI

In this paper, we propose a new technique for higher circuit speed without increase in leakage current by using active body-bias controlling technique. Conventional body-bias controlling techniques face difficulties, such as long transition time of body voltage and large area penalty. To overcome these issues, we propose a Charge Recycling Active Body-bias Controlled (CRABC) circuit scheme on SOI which enables quick control of body voltage by using simple additional circuit. The SPICE simulation results have shown that CRABC shortens delay time by 20 %, and transition time for controlling body-bias by 98 %.

A novel layout approach using dual supply voltage technique on body-tied PD-SOI

This paper presents a novel layout approach using dual supply voltage technique. In Placing and Routing (P&R) phase, conventional approaches for dual supply voltages need to separate low supply voltage cells from high voltage ones. Consequently, its layout results tend to be complex compared with single supply voltage layout results. Our layout approach uses cells having two supply voltage rails. Making these cells is difficult in bulk due to increase in area by n-well isolation or in delay by negative body bias caused by sharing n-well. On the other hand, making cells with two supply voltage rails is easy in body-tied PD-SOI owing to separation of transistor bodies by trench isolation. Since our approach for dual supply voltages offers freedom for placement as much as conventional ones for single supply voltage, exsting P&R tools can be used without special operation. Simulation results with MCNC circuits and adders have shown that our approach reduces power by 19 % and 25 %, respectively, showing almost the same delay with single supply voltage layout.

Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI

The dual supply voltage (dual-VDD) scheme reduces the active power consumption without performance degradation by using two power supply rails. However, an increase in the delay due to the scaled-down supply voltage has made assigning the lower supply voltage (VDDL) more difficult in the conventional dual-VDD scheme. We propose a technique for the dual-VDD scheme employing the Active Body-biasing Control (ABC) on PD-SOI, which increases the number of VDDL-cells owing to lowered threshold voltage. Simulation results have shown our approach effectively reduces the power consumption even at low voltage operation.

Delayed-ABC SOI for crosstalk noise repair

Crosstalk repair by gate sizing often increases the noise on adjacent wires, and results in cyclical iterations of noise repair. We propose a Delayed Actively Body-bias Controlled (D-ABC) SOI scheme for crosstalk noise repair by providing delayed forward bias to drivers. The delay between gate and body suppresses the crosstalk noise on adjacent wires. The proposed D-ABC SOI scheme has reduced the crosstalk noise by 48.5%, with 4.3% increase in the crosstalk noise on adjacent wires.