Yohei Matsumoto

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

A new method for improving the timing yield offield-programmable gate array (FPGA) devices affected by intrinsicwithin-die variation is proposed. The timing variation is reducedby selecting an appropriate configuration for each chip from a setof independent configurations, the critical paths of which do notshare the same circuit resources on the FPGA. In this article, theactual method used to generate independent multiple configurationsby simply repeating the routing phase is shown, along with theresults of Monte Carlo simulation with 10,000 samples. Onesimulation result showed that the standard deviations of maximumcritical path delays are reduced by 28% and 49% for 10% and 30%Vth variations (σ/ μ), respectively,with 10 independent configurations. Therefore, the proposed methodis especially effective for larger Vth variation and isexpected to be useful for suppressing the performance variation ofFPGAs due to the future increase of parameter variation. Anothersimulation result showed that the effectiveness of the proposedtechnique was saturated at the use of 10 or more configurationsbecause of the degradation of the quality of the configurations.Therefore, the use of 10 or fewer configurations is reasonable.

Fully-functional FPGA prototype with fine-grain programmable body biasing

A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing.

Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components

An FPGA with field-programmable Vth components can attain both high performance and low power consumption, without placement and routing constraints, by flexibly controlling the threshold voltage (Vth) of transistors. Since Vth for transistors for a specific circuit block in an FPGA is chosen from a set of Vth values defined by body bias voltage set (BBVS), adequate selection of BBVS is important in the design decision process in a field-programmable Vth method. In this paper, the effect of the selection of BBVS on static power reduction in an FPGA with field-programmable Vth components was presented. To select the optimal BBVS among several supplied body bias voltage candidates, several BBVSs are provided. The results show that the best BBVS achieves remarkable static power reduction, to as little as 1/30 the value in a conventional FPGA without performance degradation. In addition, the study on the optimal selection of body bias voltage for high-Vth transistor in a BBVS reveals that deep reverse body bias for high-Vth transistor does not necessarily offer the optimal condition, and optimization is necessary

Development of a CAD tool for 3D-FPGAs

This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A∗) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.

Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA

This paper describes a new design concept, the Body Bias Voltage Set (BBVS), and presents the effect of the BBVS on static power, operating speed, and area overhead in an FPGA with field-programmable Vth components. A Flex Power FPGA is an FPGA architecture to solve the static power problem by the fine grain field-programmable Vth control method. Since the Vth of transistors for specific circuit blocks in the Flex Power FPGA is chosen from a set of Vth values defined by a BBVS, selection of a particular BBVS is an important design decision. A particular BBVS is chosen by selecting body biases from among several supplied body bias candidates. To select the optimal BBVS, we provide 136 BBVSs and perform a thorough search. In a BBVS of less Vth steps, the deepest reverse body bias for high-Vth transistors does not necessarily result in optimal conditions. A BBVS of 0.0 V and -0.8 V, which requires 1.65 times the original area, utilizes as little as 1/30 of the static power of a conventional FPGA without performance degradation. Use of an aggressive forward body bias voltage such as +0.6 V for lowest-Vth, performance is increased by up to 10%. Another BBVS of +0.6 V, 0.0 V, and -0.8 V reduces static power to 14.06% while maintaining a 10% performance increase, but it requires 2.75-fold area.

FPGAs with Multidimensional Switch Topology

This manuscript proposes an FPGA by embedding a multidimensional switch topology onto a two-dimensional chip. We show, using Rents Rule, that this procedure reduces the number of switches. Then we propose the actual procedure and demonstrate that this does not increase metal wire density critically.

Performance comparison of 2D and 3D FPGAs using true-3D CAD tool

3-dimensional (3D) integration is imperative for the future of semiconductor devices. The 3D field-programmable gate array (FPGA) is one of the killer applications in this field because large-scale FPGA requires numerous wire segments that conventional 2D integration cannot deal with. We have developed a true-3D computer-aided design (CAD) tool for the 3D FPGA and have quantitatively compared its performance against that of a 2D FPGA. Experimental results indicate that the 3D FPGA is superior to 2D FPGA in terms of both smaller critical path delay and smaller area.

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip

First prototype flex power FPGA chip is presented. Basic concept of flex power FPGA is to control speed/power trade-off relationship flexibly by assigning the proper threshold voltage generated from body-bias control circuits to transistors. An experimental chip, which implements a power configurable block array connected in series having minimal indispensable functions to flex power FPGA, i.e. circuit configurability and power configurability, was fabricated in 90 nm standard CMOS technology with triple-well option for the first time. As evaluation results of the static power saving ability and operating speed controllability, the concept of flex power FPGA is proved.

Ship detection for automating navigational watch

Automatic navigational watch system is currently under development. Because the system should detect ships over a miles away from own ship, the depth of the field is extremely deeper than that of ordinal computer vision applications. This paper shows the results applying typical HOG (Histograms of Oriented Gradients)-SVM (Support Vector Machine) based sliding window object detector to the navigational images, and discusses the difficulties and their possible remedies.