Toshihiro Sekigawa

Demonstration, analysis, and device design considerations for independent DG MOSFETs

This paper describes a comprehensive study on the threshold voltage (V/sub th/) controllability of four-terminal-driven double-gate (DG) MOSFETs (4T-XMOSFETs) with independently switched DGs. Two types of 4T-XMOSFETs (fin and vertical) are experimentally demonstrated and their V/sub th/ controllability is thoroughly investigated in relation to the initial V/sub th/ in the DG-mode based on comprehensible modeling of the devices. Based on the investigation and simulated predictions, device design guidelines for 4T-XMOSFETs are proposed. Decreasing the workfunction of the DGs and increasing the oxide thickness of the second gate (T/sub ox2/) are preferable for improving the performance of the 4T-XMOSFET. The optimum workfunction of DGs for attaining low I/sub off(stand-by)/ and high I/sub on(active)/ under the limited V/sub g2/ condition is also proposed.

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.

Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs

We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFETs in the 40-135 nm gate length regime. It is experimentally and systematically found that the threshold voltage (V/sub th/) roll-off and subthreshold slope (S-slope) are highly suppressed as the channel SOI thickness is reduced. The experimental 40-nm gate length, 4-nm thick ultrathin SOI n-MOSFET shows the S-slope of only 75 mV and the /spl Delta/V/sub th/ of only 0.07 V as compared to the value in the case of the long gate-length (135 nm) device. Based on these experimental results, the remarkable advantage of an ultrathin SOI channel in suppressing the short-channel effects is confirmed for future MOS devices.

Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel

The FT-FinFETs with independent double gates and an ideal rectangular cross-section Si-Fin channel have successfully been fabricated by using newly developed orientation-dependent wet etching. The flexible V/sub th/ controllability by using one of the double gates as a control gate and by the synchronized driving mode operation is experimentally confirmed. The developed processes are attractive for the fabrication of the advanced separate-gates FinFET for a flexible function VLSI circuit.

Investigation of the TiN Gate Electrode With Tunable Work Function and Its Application for FinFET Fabrication

The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phi_TiN) slightly decreases with increasing nitrogen (N₂) gas flow ratio, R_N=N₂/(Ar+N₂) in the sputtering, from 17% to 100%. The experimental threshold voltage (V_th) dependence on the R_N shows that the more R_N offers the lower V_th for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different R_N showed that the more amount of nitrogen is introduced into the TiN films with increasing R_N, which suggests that the lowering of phi _TiN with increasing R_N should be related to the increase in nitrogen concentration in the TiN film. The desirable V_th shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n⁺ poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication

Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching

A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion-bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFETs, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm.

Improvement of SiO2/4H-SiC Interface Using High-Temperature Hydrogen Annealing at Low Pressure and Vacuum Annealing

The influences of high-temperature H2 annealing at low pressure (8.5×102 Pa at 1273 K) and vacuum (1× 10-4 Pa at 1273 K) annealing on capacitance-voltage (C-V) characteristics of 4H-SiC MOS structures have been investigated. H2 annealing more effectively reduced the flat band voltage shift of the 4H-SiC MOS structure than vacuum annealing. The interface state density of the 4H-SiC MOS structure after H2 annealing at 1273 K was reduced to approximately one-fifth that of the sample without H2 annealing. Secondary ion mass spectroscopy (SIMS) revealed that hydrogen accumulated at the SiO2/4H-SiC interface, and its density increased with H2 annealing temperature.

Atomically Flat 3C-SiC Epilayers by Low Pressure Chemical Vapor Deposition

We have investigated the heteroepitaxial growth of 3C-SiC on Si by low pressure chemical vapor deposition (LPCVD) using a silane-propane-hydrogen reaction gas system. By the growth at low pressure below 10 Torr, several problems arising from atmospheric pressure CVD (APCVD) were solved, namely the growth of protrusions was suppressed and thickness uniformity was improved. Moreover, atomically flat surfaces were obtained. Although the growth temperatures in the case of LPCVD were lower than those in the case of APCVD, LPCVD epilayers showed excellent crystallinity and luminescence properties, comparable with those of APCVD epilayers.

Capacitance-voltage characteristics of Semiconductor-Insulator-Semiconductor (SIS) structure

Abstract The ideal low- and high-frequency capacitance-voltage curves of a semiconductor(2)-insulator-semiconductor(1) (SIS) structure were first calculated with the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) as parameters. The effects of fixed oxide charge and interface trap charge on the low and high frequency capacitance-voltage curves were also calculated. It was found that the fixed oxide sheet charge density with its centroid and the order estimation of the interface trap charge density with its effective type in addition to the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) could be estimated from measured low and high frequency capacitance-voltage curves of an SIS structure.

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.