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Dive into the research topics where Masana Harada is active.

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Featured researches published by Masana Harada.


international symposium on power semiconductor devices and ic s | 1990

Effects of shorted collector on characteristics of IGBTs

Hajime Akiyama; Tadaharu Minato; Masana Harada; Hsinghou Pan; H. Kondoh; Y. Akasaka

Vertical insulated gate bipolar tran- sistors with various shorted collector patterns (CS- IGBT) were studied with regard to steady state and transient electrical characteristics at 25OC and 125OC, compared with a conventional IGBT. A two dimensional effect of the shorted collec- tor on the on-state voltage is found to have an ef- fect on an onset voltage of the hole injection from the collector. Furtheremore, the CS-IGBT reveals a positive temperature dependece of the on-state voltage and much less temperature dependence of the turn-off transient in contrast with the conven- tional IGBT.


international symposium on power semiconductor devices and ic s | 2001

Wide cell pitch 1200 V NPT CSTBTs with short circuit ruggedness

Hideki Nakamura; Katsumi Nakamura; Shigeru Kusunoki; Hideki Takahashi; Yoshifiuni Tomomatsu; Masana Harada

We have studied a suitable structure for 1200 V NPT-IGBTs from the viewpoint of total performance. We propose the wide cell pitch CSTBT (Carrier Stored Trench Bipolar Transistor) structure. As a result, small gate capacitance and short circuit ruggedness have been established by reducing MOS channel width. A small on-state voltage has been achieved by the carrier store effect of CSTBTs. To control the breakdown voltage and to suppress oscillation during short circuit operation, damping trench capacitors have been also prepared.


international symposium on power semiconductor devices and ic s | 1998

A design concept for the low turn-off loss 4.5 kV trench IGBT

Tetsuo Takahashi; A. Uenishi; Shigeru Kusunoki; Tadaharu Minato; H. Nakamura; Shinji Aono; Katsumi Nakamura; T. Nitta; Masana Harada

In this study, we analyze the turn-off behaviour of high voltage trench insulated gate bipolar transistors (IGBTs) by means of numerical simulation. There are two types of trade-off relationship in the turn-off process. The first relationship is between the voltage-rising process and the tail-current process. This depends on the carrier distribution in the on-state and the MOS channel electron current. The second relationship is between the impact ionization and the MOS channel electron current. In this paper, we propose a new IGBT structure that has the minimum turn-off loss, the optimum carrier distribution in the on-state and the optimum Miller-capacitance.


international symposium on power semiconductor devices and ic's | 1997

A simple and effective carrier lifetime evaluation method with diode test structures in IGBT

Shinji Aono; Tetsuo Takahashi; Katsumi Nakamura; Hideki Nakamura; Akio Uenishi; Masana Harada

A simple and effective method of evaluating the carrier lifetime of a power device chip is proposed. In this method, Test Element Groups (TEGs) of diodes fabricated in the periphery of an Insulated Gate Bipolar Transistor (IGBT) chip were used as carrier lifetime monitors of the IGBTs n/sup -/ layer. The measured forward voltage drops (V/sub f/) of the diode-TEGs were compared with simulated V/sub f/ and the lifetime was determined from the lifetime parameter of simulations. The estimated lifetime value was verified by the reverse recovery current characteristic.


Archive | 1996

Power semiconductor device with insulated trench gate and manufacturing method thereof

Masana Harada; Tadaharu Minato; Katsumi Nakamura; Tetsuo Takahashi


Archive | 1996

Method of making an IGBT device

Masana Harada; Tadaharu Minato; Katsumi Nakamura; Tetsuo Takahashi


Archive | 2000

Power semiconductor diode with insulated gate and manufacturing method thereof

Masana Harada; Tadaharu Minato; Katsumi Nakamura; Tesuo Takahashi


Archive | 2001

Semiconductor with pnpn structure

Tetsuo Takahashi; Katsumi Nakamura; Tadaharu Minato; Masana Harada


Archive | 2000

IS~SD*ZOOO. May ZZ-Z~. I ouiouse. prance Advantages of Thick CVD Gate Oxide for Trench MOS Gate Structures

Katsumi Nakamura; Shigeru Kusunoki; Hideki Nakamura; Masana Harada


Archive | 1996

Diode de type pin et son procédé de manufacture

Masana Harada; Tadaharu Minato; Katsumi Nakamura; Tetsuo Takahashi

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