Tadaharu Minato

Effects of shorted collector on characteristics of IGBTs

Vertical insulated gate bipolar tran- sistors with various shorted collector patterns (CS- IGBT) were studied with regard to steady state and transient electrical characteristics at 25OC and 125OC, compared with a conventional IGBT. A two dimensional effect of the shorted collec- tor on the on-state voltage is found to have an ef- fect on an onset voltage of the hole injection from the collector. Furtheremore, the CS-IGBT reveals a positive temperature dependece of the on-state voltage and much less temperature dependence of the turn-off transient in contrast with the conven- tional IGBT.

Making a bridge from SJ-MOSFET to IGBT via RC-IGBT structure Concept for 600V class SJ-RC-IGBT in a single chip solution

Through the simulation, a concept for the next generation MOSFET or IGBT as a single chip solution by combining Super Junction MOSFET (SJ-MOSFET) with Reverse Conducting IGBT (RC-IGBT) is presented. Since the MOSFETs fundamental trade-off relationship between Ron,sp and turn-off loss Eoff is much better than IGBTs, we focus how to push up a connection collector current density Jconnect where SJ MOSFETs output I-V curve touches the IGBTs one and found out the good combination for an N-drift and an N-buffer. This proposed device has an enough Unclamped Inductive Switching (UIS) capability as the SJ-MOSFETs SOA and acceptable dynamic characteristics as the IGBT or the FWD.

A design concept for the low turn-off loss 4.5 kV trench IGBT

In this study, we analyze the turn-off behaviour of high voltage trench insulated gate bipolar transistors (IGBTs) by means of numerical simulation. There are two types of trade-off relationship in the turn-off process. The first relationship is between the voltage-rising process and the tail-current process. This depends on the carrier distribution in the on-state and the MOS channel electron current. The second relationship is between the impact ionization and the MOS channel electron current. In this paper, we propose a new IGBT structure that has the minimum turn-off loss, the optimum carrier distribution in the on-state and the optimum Miller-capacitance.

Future trend of Si power device

As a FOM (Figure Of Merit), the power density of a power module has grown in an almost constant ratio for the past 20 years in the field of power electronics. This progress has been achieved by the joint development of power chips and a package. A combination of an IGBT (Insulated Gate Bipolor Transistor) and an FWD (Free Wheeling Diode) is the most frequent combination of power chips for a power module. The progress of both IGBT and diode is based not only upon the development of device structures but also upon the progress of the wafer process technology, which is derived from a LSI (Large Scale Integrated circuit) process and optimised for the power device. The package technology for power devices is uniquely developed for high reliability even for high power density application. This paper reports both the power chip and the package technologies up to the latest generation for the IGBT power module.

Study about Si wafer (mother) material for high speed LPT-CSTBT™ based on electrical and physical analysis

In the IGBT as bipolar silicon power device, it is widely used a carrier lifetime control technique, i.e. an inducing a carrier trap level within the silicon band gap by an electron beam irradiation with a post thermal annealing. Sometimes, the electrical characteristics tend to change after the long term usage at high current density, because DC current stress of the high current density affects as if annealing out process at the high temperature. Hence it is necessary to eliminate several unstable shallow trap levels by thermal annealing in wafer process for maintaining the electrical characteristics stabilities. On the other hand, the trap levels originated in a very small amount of residual carbon (C) and/or oxygen (O) sometimes make the stabilities of electrical characteristics complicated. When we analyze this phenomenon, Photo-Luminescence (PL) is easy to grasp tendencies and is better than Cathode-Luminescence (CL). In this paper, through PL, we investigated silicon wafers of Floating Zone (FZ) and Magnetic Czochralski (MCZ) and studied the relationship between electrical characteristics and residual C &/or O in silicon mother materials which are the different of the diameter and/or the manufacturing methods.

Simple simulation approach for the first trigger step of SEB (single event burn-out) based upon physical analysis for Si high voltage bipolar device

Through the physical analysis, the first and minimum destruction point of the power semiconductor chip is precisely identified as around the main pn junction. It well agrees with the Impact Ionization (I/I) peak enhanced by an electric field crowding. A simple device simulation approach, which uses a visible light approximation (optical generation) instead of a high energy radiation ion, is effective to trace the SEB phenomenon. Several fundamental settings were studied to simulate the experimental results.

Physical analysis of carrier lifetime controlled IGBT [II]

For IGBTs, there are strong requirements for high current density usage from the cost reduction point of view and high speed operation from the system efficiency point of view. Strong carrier lifetime control is needed to reduce a turn-off loss (Eoff) of IGBT for high frequency usage. It seems to be insufficient for our previous report [1–2] to deeply understand about correlation between electric characteristics and Cathode Luminescence (CL), which stands for free conduction carrier trap levels inside Si band structure. Clearer physical model is necessary to improve an agreement for both high current density and high speed operation. Therefore, we applied another analysis method of PL (Photo Luminescence) to ensure the physical model for carrier lifetime controlling method to combine relatively heavy dose of Electron Beam (EB) irradiation and high temperature thermal annealing.