Shigeru Kusunoki

Three dimensional IC for high performance image signal processor

The three-dimensional (3-D) image processing test IC designed with parallel processing architecture is fabricated. The device consists of 5-by-5 array of photosensors, 2-bit CMOS A-to-D converters, 40 arithmetic logic units (ALU) and shiftregisters arranged in a 3-layer structure. The total operation from photosensor on top layer to ALU on bottom layer is confirmed, and it is also demonstrated the feasibility of very high speed system operation with the implement of parallel processing. This device gives a clear image of the intelligent image processor on one chip as a future application of 3-D ICs.

The effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties

We have studied the effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties in detail for the surface channel PMOS below 0.25 /spl mu/m. It was founded that boron penetration through the gate oxide film can be effectively suppressed by nitrogen implantation into P/sup +/ poly-silicon gate. Moreover the generation of interface states and traps can be also reduced by nitrogen implantation. Therefore the resistance against the hot carrier injection can be dramatically improved. These improvements would be due to the incorporation of nitrogen into gate oxide film and the reduction of boron and fluorine atoms in the gate oxide film.<<ETX>>

Impact of surface proximity gettering and nitrided oxide side-wall spacer by nitrogen implantation on sub-quarter micron CMOS LDD FETs

We propose an advanced sub-quarter micron CMOS process for ultra shallow junctions and high reliability using a new nitrogen implantation technique. Nitrogen atoms implanted into the source/drain for NMOSFETs and PMOSFETs can suppress impurity diffusion and leakage current, since not only can nitrogen atoms occupy the diffusion path of arsenic and boron atoms but also the secondary defects induced by nitrogen implantation can act as a surface proximity gettering site. Moreover, this technique can remarkably suppress the hot carrier degradation for CMOS LDD FETs, since the segregation of nitrogen at interface between the substrate and the side-wall SiO/sub 2/ can reduce the interface state generation under the side-wall spacer.

0.15 /spl mu/m CMOS process for high performance and high reliability

We have developed a novel 0.15 /spl mu/m CMOS process for high performance and high reliability, consisting of mixing the CoSi/sub 2/-Si interface using Si/sup +/ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using these processes, the propagation delay time of 21 psec/stage was obtained for a 0.15 /spl mu/m CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.<<ETX>>

Characteristics of a 1200 V CSTBT optimized for industrial applications

The design of power semiconductor chips has always involved a trade-off between switching speed, static losses, safe operating area and short-circuit withstanding capability. This paper presents an optimized structure for 1200 V IGBTs from the viewpoint of all-round performance. The new device is based on a novel wide cell pitch carrier stored trench bipolar transistor (CSTBT). Unlike conventional trench gate IGBTs, this structure simultaneously achieves both low on-state voltage and the rugged short-circuit capability desired for industrial applications.

Highly reliable 0.15 /spl mu/m MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantation

An advanced nitrogen implantation technique is proposed. The new technique can suppress remarkably the hot carrier degradation. Since the generation of interface states can be reduced by the incorporation of nitrogen at the interface between a substrate and SiO/sub 2/ spacers. Moreover, the ultra shallow junction without the increase in leakage current can be formed by nitrogen implantation into the source/drain. Since the secondary defects induced by nitrogen implantation can act as a surface proximity gettering (SPG) site.

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.<<ETX>>

Advantages of thick CVD gate oxide for trench MOS gate structures

We have done research for the purpose of improving the reliability of trench MOS gate devices that utilize trench gate oxide over 10 nm in thickness. This paper reports, for the first time, that the CVD gate oxide (CGO) film is much more effective as a gate dielectric for use in trench MOS gate devices than the thermal oxide widely used in the SiO/sub 2/ gate dielectric of MOS gate devices. Our results show that the electrical characteristics (leakage characteristic and Time-Zero Dielectric Breakdown characteristic), the reliability and current drivability of trench MOS gate devices can be dramatically improved by CVD gate oxide (especially oxynitride CGO). These improvements are caused by the excellent uniformity of thickness and the good quality of gate oxide which formed on an inner trench with the specific geometrical factor. From the viewpoint of insuring the reliability for large trench capacitor area, this new CGO dielectric is a promising candidate for trench MOS gate power devices.

A high performance and highly reliable dual gate CMOS with gate/n/sup -/ overlapped LDD applicable to the cryogenic operation

A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n/sup +/ poly gate and a surface channel PMOS with p/sup +/ poly gate whose source/drain and gate were salicided with low-resistance TiSi/sub 2/. The gate/n/sup -/ overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.<<ETX>>