Masanori Hayashikoshi

A 34ns 16MbDRAM with controllable voltage down convertor

The centrally active cholinesterase inhibitor physostigmine induces a behavioral syndrome which is thought to represent a model of spontaneous depression. In the present acute trial in 6 healthy volunteers, this model depression was accompanied by clearcut cardiovascular, metabolic and neuroendocrine phenomena of stress. The extent of the changes from baseline, however, scarcely correlated between the behavioral and physiologic phenomena. The behavioral and physiological phenomena could not be antagonized by brofaromine, a putative antidepressant reversibly and selectively inhibiting monoamine oxidase A (MAO-A), contrasting to the complete inhibition by the central cholinolytic scopolamine. This is further evidence that antidepressant efficacy depends on long-term adaptive changes secondary to the enhancement of aminergic neurotransmission rather than this enhancement itself.

High speed page mode sensing scheme for EPROMs and flash EEEPROMs using divided bit line architecture

A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved

A Testing Technique for ULSI Memory with On-chip Voltage Down Converter

Highly reliable testing techniques for ULSI memory with on-chip voltage down converter are established. These techniques are an accurate tuning of internal-Vcc (intVcc) and a wide operating margin test using a new stress mode. The accurate tuning of intVcc is achieved by the trimming method with the measuring of on-chip monitor device characteristics during repairanalysis tests. The wide operating margin test is executed using a new stress mode in which intVcc can be set to the various voltage conditions at the wafer sort tests (WT) and the final shipping tests (FT).