Yasushi Terada

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V/sub cc/ and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 /spl mu/m, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8/spl times/1.6 /spl mu/m/sup 2/ and the chip measures 5.8/spl times/5.0 mm/sup 2/. The divided bit line structure realizes a small NOR type memory cell. >

Negative heap pump for low voltage operation flash memory

A negative heap pump circuit which is free from the threshold voltage restriction has been described. The proposed charge pump which heaps up the coupling capacitor must be a key technology for low power operative flash memories.

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 mu m*2.0 mu m and a chip size of 6.5 mm*18.4 mm were achieved using a simple stacked gate cell structure and 0.6- mu m CMOS process. >

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 mu m design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7*8 mu m/sup 2/ and the chip size is 5.55*7.05 mm/sup 2/. The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC. >

A new decoding scheme and erase sequence for 5 V only sector erasable flash memory

The authors describe a decoding scheme and erase sequence for a 5-V-only sector-erasable flash memory. A source line decoder eliminates the erase disturb problem and lowers the power consumption. The maximum switching voltage is reduced to 10 V, which makes possible a tight word line pitch for a 64-Mb flash memory. Narrow threshold voltage distribution of erased memory cells is obtained by programming after erase.<<ETX>>

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs. >

A high-speed parallel sensing architecture for multi-megabit flash E/sup 2/PROMs

A high-speed parallel sensing architecture for high-density 5-V-only flash E/sup 2/PROMs is described. A source-biasing technique enhanced the cell current while minimizing the read disturbance problem. Flip-flop-type differential sense amplifiers are arranged between every two pairs of bit lines, so that half the memory cells on the same work line are sensed simultaneously. Self-time dynamic sensing was developed for high speed and stable sensing and also decreased read disturbance and operating current. Simulated results show that a sub-10- mu A cell current is successfully sensed in 40 ns. In the program mode, the differential amplifier acts as a column latch, which substantially reduces the chip size. >

Row-redundancy scheme for high-density flash memory

Flash memory is recognized as one of the key devices of personal digital assistant and other portable equipment. Rapid expansion of the market is expected because it is estimated that the cost of flash memory will eventually be lower than that of DRAM. However, to achieve low cost, a highly efficient redundancy scheme must be implemented for the chip. Although the same column redundancy scheme used in DRAM and SRAM can be applied to flash memory, conventional row redundancy in which defective word lines are replaced by spare word lines is not suitable. In flash memory, all memory cells in the erase block must be programmed before the erase pulse is applied to the memory array to avoid over-erasure. If the replaced word line is shorted to the adjacent word line, memory cells on the defective word line cannot be programmed even if the replaced word line is selected because the word line is grounded through the adjacent word line.<<ETX>>

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs

A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0- mu m triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 mu m*8 mu m, and the chip is 7.73 mm*11.83 mm. The device is configured as either 128 k*8 or 64 k*16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.<<ETX>>