Hideaki Arima

A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structure

A 3.6 mu m/sup 2/ 5 V only 16 Mb flash EEPROM cell was obtained using a simple stacked gate structure and a conventional 0.6 mu m CMOS process. A single 5 V power supply operation of the simple stacked gate cell was realized by optimizing the well impurity concentration and the drain structure and using a gate negative biased erasing operation. It is also shown that the gate negative biased erasing operation mode is very effective in improving the cell endurance characteristics.<<ETX>>

A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET for high current drivability and threshold voltage controllability

A novel source-to-drain nonuniformly doped channel (NUDC) MOSFET was investigated theoretically and experimentally. Using an analytical model, it is verified that the mobility of the NUDC MOSFET is increased as compared with that of the conventional channel MOSFET. Also, the V/sub th/ lowering of the NUDC MOSFET is suppressed as compared with that of the conventional channel MOSFET. The NUDC MOSFET was fabricated by the oblique rotating ion implantation technique, and the theoretical predictions were confirmed experimentally.<<ETX>>

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 mu m*2.0 mu m and a chip size of 6.5 mm*18.4 mm were achieved using a simple stacked gate cell structure and 0.6- mu m CMOS process. >

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 mu m design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7*8 mu m/sup 2/ and the chip size is 5.55*7.05 mm/sup 2/. The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC. >

A novel stacked capacitor cell with dual cell plate for 64 Mb DRAMs

The authors propose a novel stacked capacitor cell with dual cell plate (DCP cell) for 64-Mb DRAMs. The major advantage of this cell is that the dual cell plates completely surround the whole surface of the storage polysilicon, and the storage capacitance of this cell increases significantly compared to the conventional stacked capacitor cell. For a 1.3- mu m/sup 2/ cell, the DCP cell should achieve a storage capacitance of more than 25 fF. The experimental results indicate that the DCP cell can realize the 64-Mb DRAMs and 1.3- mu m/sup 2/ cell area using the 0.3- mu m design rule.<<ETX>>

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs. >

A novel process technology and cell structure for mega bit EEPROM

A high-performance CMOS technology and cell structure for a megabit EEPROM are described. A novel EEPROM (electrically erasable programmable read-only memory) cell called a stacked floating gate with self-aligned tunnel region (SSTR) cell has been developed. A merged signal transistor structure has been developed to reduce the cell size. A sufficient cell threshold window is obtained in 2 ms at 16 V in both write and erase operation, using Fowler-Nordheim electron tunneling between the floating gate and the n/sup +/ region. The endurance of the cell is greater than 100000 erase/write cycles. An SSTR cell with a capacitive coupling ratio of 0.83 and a cell area of 30.4 mu m/sup 2/ has been implemented in a 1-Mb EEPROM.<<ETX>>

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs

A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0- mu m triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 mu m*8 mu m, and the chip is 7.73 mm*11.83 mm. The device is configured as either 128 k*8 or 64 k*16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.<<ETX>>