Shoun Matsunaga

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.

Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices

A compact ternary content-addressable memory (TCAM) cell of 3.15 µm2 with a 0.14 µm complementary metal oxide semiconductor process is realized by the use of nonvolatile magnetic tunnel junction (MTJ) devices with spin-injection write. This TCAM cell based on logic-in-memory architecture with nonvolatile MTJs needs no standby power, yet allows instant shut-down of the supply voltage without data backup to an external nonvolatile device.

A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism

This paper introduces a self-timed overlapped search mechanism for high-throughput content-addressable memories (CAMs) with low search energy. Most mismatches can be found by searching the first few bits in a search word. Consequently, if a word circuit is divided into two sections that are sequentially searched, most match lines in the second section are unused. As searching the first section is faster than searching an entire word, we could potentially increase throughput by initiating a second-stage search on the unused match lines as soon as a first-stage search is complete. The overlapped search mechanism is realized using a self-timed word circuit that is independently controlled by a locally generated control signal, reducing the power dissipation of global clocking. A 256 x 144-bit CAM is designed under in 90 nm CMOS that operates with 5.57x faster throughput than a synchronous CAM, with 38% energy saving and 8% area overhead.

Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory

A novel 7-transistor/2-magnetic-tunnel-junction (7 T-2MTJ) cell circuit is proposed for a high-speed and compact nonvolatile ternary content-addressable memory (TCAM). Since critical path for switching in the TCAM cell circuit, which determines the performance of the TCAM, is only a single MOS transistor, switching delay of the TCAM word circuit is minimized. As a result, 270 ps of switching delay in 144-bit TCAM word circuit is achieved under a 90 nm CMOS/MTJ technology with magneto-resistance ratio of 100%, which is about two times faster than a conventional CMOS-based TCAM.

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Towards a low search-energy nonvolatile ternary content-addressable memory (TCAM), we propose a novel nine-transistor/two-magnetic-tunnel-junction (9T–2MTJ) nonvolatile TCAM cell circuit with a high-speed accessibility. Since critical path for switching in the TCAM cell circuit is only a single metal-oxide-semiconductor (MOS) transistor, switching delay of the TCAM word circuit is minimized. As a result, the worst-case switching delay of 0.22 ns is achieved in a 144-bit word circuit under a 90 nm complementary MOS (CMOS)/MTJ technology, which is about 2.6 times faster than that of a conventional CMOS-based TCAM. In order to minimize the active power dissipation in the proposed TCAM, a multi-level segmented match-line scheme that maximally brings inessential cells to standby state is also applied to the 9T–2MTJ-cell-based word circuit. Finally, low search-energy of 0.73 fJ/bit/search is achieved in a 144-bit × 256-word nonvolatile TCAM together with eliminating standby power using nonvolatility.

Fine-Grained Power-Gating Scheme of a Metal–Oxide–Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory

A fine-grained power-gating scheme combining metal–oxide–semiconductor (MOS) transistors with magnetic-tunnel-junction (MTJ) devices, where storage data still remains even if the power supply is cut off, is proposed for an ultra low-power bit-serial ternary content-addressable memory (TCAM). Once a mismatched result is detected in a sequence of a bit-level equality-search operation, the power supply of all the cells in the word circuit is cut off, which greatly reduces the standby power dissipation in the word circuit. The standby power dissipation of the proposed TCAM in the standby mode is reduced to about 1.2% in comparison with that of a complementary MOS (CMOS)-only-based TCAM. Moreover, the power-delay product of the proposed TCAM is reduced to 15.5% in comparison with that of the corresponding CMOS-only-based TCAM.

High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism

This paper introduces a reordered overlapped search mechanism for high-throughput low-energy content-addressable memories (CAMs). Most mismatches can be found by searching a few bits of a search word. To lower power dissipation, a word circuit is often divided into two sections that are sequentially searched or even pipelined. Because of this process, most of match lines in the second section are unused. Since searching the last few bits is very fast compared to searching the rest of the bits, we propose to increase throughput by asynchronously initiating second-stage searches on the unused match lines as soon as a first-stage search is complete. In our circuit implementation, each word circuit is independently controlled by a locally generated timing signal rather than a global signal. This allows the circuits to be in the required phase for their own local operation: evaluate or precharge, instead of having to synchronize their phase to the rest of the word circuits, which greatly reduces the cycle time. As a design example, a 128 × 64-bit CAM is implemented and evaluated by HSPICE simulation under a 90 nm CMOS technology. The proposed asynchronous CAM operates 5.98 times faster than a synchronous CAM with 14.2% smaller energy dissipation. The post-layout proposed CAM achieves 385-ps cycle delay time and 0.773 fJ/bit/search and is also evaluated under different corner conditions and PVT variations to guarantee it operates properly.

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme

A perpendicular magnetic-tunnel-junction (MTJ)-based 2T-2R ternary content-addressable memory (TCAM) cell is proposed for a high-density nonvolatile word-parallel/bit-serial TCAM. The use of MOS/MTJ-hybrid logic makes it possible to implement a compact nonvolatile TCAM cell with 2.5 μm2 of a cell size in a 0.14-μm CMOS and a 100-nm perpendicular-MTJ technologies. By reversed-current reading through the perpendicular MTJ device, tolerability of read disturb is greatly enhanced. Moreover, fine-grained power gating based on bit-level equality-search scheme achieves ultra-low activity rate of 4.1% in a fabricated 72-bit × 128-word nonvolatile TCAM, which results in ultra-low active power and standby power.

Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme

A novel compact and static-power-free nonvolatile ternary content-addressable memory (TCAM) cell, where two-bit nonvolatile magnetic tunnel junction (MTJ) devices are stacked over the comparison logic circuit, is proposed for a high-density and ultra low-energy fully-parallel TCAM. The use of nonvolatile logic-in-memory circuit architecture makes it possible to realize 6T-2MTJ TCAM cell structure. The 144-bit word match-line is divided into two parts (first 10-bit and last 134-bit parts), which greatly reduces the dynamic power dissipation with small overhead of the switching delay. In fact, it is evaluated by the HSPICE simulation under a 90nm CMOS/MTJ technology that the search energy (power-delay product) of the proposed TCAM is reduced to 16 percent in comparison with that of a nonvolatile TCAM without using a segmented match-line scheme.