Masao Morimoto

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

Scaling of process technology is inevitably accompanied by the increase of local variation in transistor characteristics, which has been deteriorating the operation margin of SRAM. This trend necessitates assist circuits for SRAM to increase the immunity against variations, and many papers in this area [1-4] have been published. In this paper, we present an assist circuit suitable for the SRAMs in 20nm generation. Figure 13.3.1 compares local variations of SRAM cell transistors, pass-gate NMOS (PG), pull-down NMOS (PD) and pull-up PMOS (PU) for 28 and 20nm, showing degradation as the process advances. Noticeably, the NMOS transistors become worse than PMOS, which causes degradation in SRAM operating margin since SRAM characteristics such as static noise margin (SNM) are more sensitive to NMOS than PMOS. Figure 13.3.1 also shows the operational window enclosed by read and write immunity against local variations in 28 and 20nm. This indicates assist circuits must perform beyond the level established in previously published work to address SRAM variation in advanced technology nodes. Lowering wordline (WL) voltage level is one of the read-assist approaches. Lowering the supply voltage of PU in a cell (ARVDD) and negative bitline (BL) techniques are known to be effective for the write operation. These techniques, however, have side-effects: lowering the WL voltage degrades write margin and lowering ARVDD leads to higher power consumption and a long cycle-time. Furthermore, the negative BL technique can cause write errors in non-selected columns. Thus, it is necessary to select which assist technique should be applied depending on each process technology. In addition, the SRAM used in production generally include single-port SRAM (SP-SRAM) and dual-port SRAM (DP-SRAM), so the assist circuits to be applied should be effective for whole SRAM family.

A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation

A multi-stage replica bitline technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed. Applied to a 288-kbit SRAM of the 40-nm process node, this technique achieves 6.1% access time reduction by reducing the sense-amplifier timing variation by 43%.

A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS

A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.

16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM macros with wordline overdriven assist

We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Test-chip measurements confirm improved minimum operating voltage (Vmin), standby leakage current, and access time compared to planar bulk CMOS. The proposed assist circuit improves Vmin by 50 mV and improves read-access-time by more than 1.5 times in 256-kbit SRAM macros. Read current (Iread) dependence against the fin diffusion length was observed. An extra design guard-band is needed to provide a reliable operation margin.

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

We propose low-leakage current embedded SRAMs with high-performance for mobile applications. The proposed SRAM has two standby modes depending on temperature; one is a low-voltage resume-standby mode to reduce the standby current (ISTBY) more effectively at room temperature, and the other is the conventional resume-standby to reduce ISTBY effectively at high temperature. These schemes are implemented in a single SRAM macro with an all-digital current comparator (ADCC) that chooses either mode by monitoring ISTBY automatically. ADCC has a time to digital converter (TDC) which is suitable for leakage measurement. Moreover, the proposed monitoring sequence can compensate the error of the measurement caused by the variation of the MOSFETs. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 kb SRAM achieves 0.41 μA standby leakage which is half of the conventional value. This SRAM also realizes a high-speed operation with an access time of 420 ps.

2RW dual-port SRAM design challenges in advanced technology nodes

We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.

A 5.92-Mb/mm 2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry

We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which enables 2-read/write (2RW) operation within a clock cycle. The data sequencer for address/data latch and double output sense amplifier realize the simulations read-read or write-write operation. We designed and implemented a 512-kb pseudo DP SRAM macro based on 28-nm low-power bulk CMOS technology. Our design achieved the bit density of 5.92 Mb/mm2, which is the highest ever reported. Measured data at 1.0 V supply voltage shows 1.05 ns read-access-time for one port and 2.37 ns for another port, respectively. Area overhead of the proposed circuitry is only 3.2% compared to the original SP SRAM macro.

1.8 Mbit/mm 2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology

A new bit-cell (BC) layout for ternary content-addressable memory (TCAM) is developed in a 16 nm Fin-FET process. The proposed BC is 15.8% smaller than the conventional BC. We design a 10kb TCAM macro which achieves the highest density of 1.8 Mbit/mm2. Measurement shows that total active power in our proposed macro is 8% less than that in the conventional one. A 484 ps of search access time is observed at 0.8 V, which marks the world fastest operation cycle of 1.25 G search per second at this time.

Embedded SRAM designs for enhancing performance, power and area (PPA) in 16 nm FinFET technology

We demonstrate SRAM circuit design techniques for enhancing performance, power and area (PPA) in 16 nm FinFET technology. The wordline overdrive (WLOD) assist circuitries with dual power rail are introduced for not only 6T single-port SRAM bitcell but also for 8T dual-port bitcell, improving minimum operating voltage (Vmin) by enhancing write-abilities. The read access times are also improved by WLOD. We also implement a high-density 2-port SRAM using 6T bitcell with double pumping scheme, enabling about 2× higher density than conventional 8T bitcell design. The resume standby circuit, which is adoptively controlled the bias of VSS source lines in cell arrays, is introduced for reducing leakage power. The measured silicon data show that the Vmin, read access time, and standby power are improved by up to 45%, 50%, and 80%, respectively.