Yukihiro Urakawa

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz. >

An 8 ns 1 Mb ECL BiCMOS SRAM

A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<<ETX>>

Characterization of speed and stability of BiNMOS gates with a bipolar and PMOSFET merged structure

A base and drain merged bipolar-PMOSFET (BiPMOS) structure was examined. A latch-up phenomenon in this structure associated with a parasitic PNP bipolar was investigated and verified experimentally and analytically. From the standpoint of stability in circuit operation a latch-up-free structure was considered. To evaluate the contribution of this technology to circuit speed performance, the structure was applied to a BiNMOS gate. It was found that the delay time if a merged BiNMOS gate was improved by 10-20% compared with that of the conventional BiNMOS gate. Moreover, at a fan-out of 1, this gate achieved a higher speed than the CMOS gate.<<ETX>>

A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit

A 7.07 mm2 synthesizable streaming processing unit (SPU) is fabricated in a 65 nm CMOS technology with 8 level copper layers. It is migrated from its original custom design to a synthesizable design to get higher design portability. New features are a new floor plan, height optimized standard cell library, local clock generator cloning and adaptive wire width control. Its logic area is 30% smaller than the full custom designed SPU in the same process generation. Correct functional operation is realized in 4 GHz at 1.4 V.

The Design of Scaled-Down Submicron 1Mb ECL/TTL BiCMOS SRAMs

INTRODUCTION BiCMOS scalability problem is considered to be serious in submicron generation devices because BiCMOS combination logic gates lose their speed advantage to CMOS logic gates as an external supply voltage is scaled-down to 3.3V [1], Actually for CMOS logic gates, external 3.3V supply voltage has various merits in the light of hot-carrier induced MOSFET degradation, time-dependent dielectric breakdown (TDDB) of gate oxide, power-reduction and so on. However, it is disadvantageous that 3.3V supply voltage devices are not compatible to former generation devices of 5V power supply. This paper will describe 5V-only BiCMOS SRAM architecture covering from 0.8jim to 0.5|im design rules and its application to lM-bit ECL/TTL SRAMs [2,3]. Two-way BiCMOS internal voltage supply, together with newly developed interface circuits, prevents MOSFET gate-drain voltage exceeding breakdown voltage to assure MOSFET reliability, and can optimize the oxide thickness so as to minimize the gate delay.

SiP2.0: What, when, and how?

Up to now, SiP integration is widely used to increase chip integration density as well as flexibility of combination in heterogeneous devices. Emerging integration and stacking technologies such as 3D integration, TSV (Through Silicon Via), die-to-die proximity communications, EAD (Embedded Active Devices) are becoming greater attention. If we call the first generation SiP integration as “SiP1.0”, what is “SiP2.0” ? When and how is it practical? Each panelists will give their anticipation of future SiP, or “SiP2.0”. This panel talk is not an “A vs. B” type of debate, but more like an evening talk where each panelist presents their visions on the next generation SiP.

3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs

The authors propose and discuss sense amplifiers suitable for low voltage operation. Compared with a conventional current sensing scheme, the hierarchical voltage sensing scheme reduces sensing delay by 39% and improves functional minimum voltage to 1.8 V, which is sufficiently low for a 3.3-V static RAM (SRAM). High-speed sensing techniques for 4-Mb VLSI SRAMs and beyond, and performance of a 9-ns, 4-Mb transistor-transistor-logic input/output SRAM implementing one of these sense amplifiers, are also presented.<<ETX>>