Masatake Nakano

Study of HF Defects in Thin, Bonded Silicon-on-Insulator Dependent on Original Wafers

To study the origin of HF defects in thin, bonded silicon-on-insulator (SOI) wafers fabricated by the plasma assisted chemical etching (PACE) process, the dependence of HF defects on original wafers [wafers fabricated by Czochralski method (CZ wafers), hydrogen-annealed CZ wafers and epitaxial wafers] was investigated. It was shown that HF defect density was affected by the type of original wafer used, and no HF defect was detected when epitaxial wafers were used as bond wafers. HF defects were detected on 0.2 µm or thinner SOI wafers with CZ wafers. Crystal originated particles (COPs) at SOI and buried oxide (SOI/BOX) interface were found to be the main origin of HF defects by inspecting light point defects (LPDs) at the SOI/BOX interface.

Heavy-Metal (Fe/Ni/Cu) Behavior in Ultrathin Bonded Silicon-On-Insulator (SOI) Wafers Evaluated Using Radioactive Isotope Tracers

The behavior of Fe, Ni and Cu in bonded silicon-on-insulator (SOI) wafers thinned down to 0.5 µm by plasma-assisted chemical etching (PACE) was investigated for the first time by the radioactive isotope tracer method, which can avoid the evaluation errors due to contamination during sample preparation or analysis. When ultrathin bonded SOI wafers without an intentional gettering site were contaminated with Fe or Ni from the surface, Fe and Ni did not diffuse into the substrate through the buried oxide (BOX) layer after annealing in N2(2%O2) ambient at 900°C and 700°C, respectively. Cu easily diffused into the substrate through the BOX layer after annealing at 700°C for 60 min, and was captured at the bonding interface. It was found that the behavior of Ni, which exhibits the same diffusivity in Si as does Cu, was quite different in ultrathin bonded SOI wafers from that in bulk Si wafers due to the BOX layer of the SOI structure.

SOI substrate solutions for recent advanced device applications

SOI substrate technology for recent advanced device applications is reviewed from a standpoint of a dedicated wafer supplier. A structure of Si thin film on sapphire (SOS) has been used for device development and manufacturing from 1970s. Currently a SOI substrate of Si/SiO2/Si structure is widely used for industrial applications.

Effective KOH Etching Prior to Modified Secco Etching for Analyzing Defects in Thin Bonded Silicon on Insulator (SOI) Wafers

The modified Secco etching which was developed for detecting threading dislocations in separation by implanted oxygen (SIMOX) wafers showed etch pits with a density of 103–106/ cm2 when it was applied to bonded silicon on insulator (SOI) wafers thinner than 1 µ m produced by the plasma assisted chemical etching (PACE) process including touch polishing. When these pits were observed, a group of pits appeared as a scratch pattern. Also the density of pits was dependent on the remaining SOI thickness after the first diluted Secco etching in the modified Secco etching process. These results indicated that the density of defects had a certain distribution in the SOI thickness direction and that the defects were different from threading dislocations which reached buried oxides from the surface. In order to observe the distribution of defect density in the SOI depth direction, KOH etching was utilized prior to the modified Secco etching. Using this method, it was found that surface defects were predominant and bulk defects were also present in thin bonded SOI layers.