Yoichiro Kurita

A novel "SMAFTI" package for inter-chip wide-band data transfer

A package structure with inter-chip connection is proposed for broadband data transfer and low latency electrical communication between a high-capacity memory and a logic device interconnected by a feedthrough interposer (FTI) featuring a fine-wiring pattern and ultra-fine-pitch through vias. The FTI is formed on a silicon wafer using a photolithography process to realize fine vias and fine wiring patterns. This structure enables over a thousand inter-chip connections and a high pin count in the logic device. This paper describes the concept, structure, process, and experimental results of prototypes of this package called SMAFTI (SMArt chip connection with FeedThrough Interposer). This paper also reports the results of intermetallic compound analysis and thermal cycle test (TCT) that were performed to confirm the fundamental reliability of this novel inter-chip connection structure

Fan-Out Wafer-Level Packaging with highly flexible design capabilities

We have developed a new Fan-Out Wafer-Level Packaging (FO-WLP) technology with flexible design capabilities for multilayer fan-out redistribution layers (RDLs) connected to the fine-pitch I/O pads of chips. The prototype of a 2.0 mm × 2.0 mm FO-WLP with 25-pin land grid array (LGA) including a 1.6 mm × 1.6 mm microcontroller chip was fabricated and evaluated. Board-level reliability was also confirmed using 5.0 mm × 5.0 mm FO-WLP. This technology is suited for applications in extremely small microcomputer chip/system packaging for ubiquitous computing.

SMAFTI package with planarized multilayer interconnects

A hybrid multilayer interconnect process and high-throughput die-to-wafer bonding technology were developed and introduced into the SMAFTI (SMArt chip connection with FeedThrough Interposer) package. The fine circuit layer FeedThrough Interposer (FTI) was fabricated between memory and logic dice and offers superior power/signal integrity, allowing over a thousand 3-D inter-chip connections through ultra-fine-pitch feedthrough vias. The unique fabrication processes of the multilayer FTI include a multilayer buildup process on a silicon wafer, filling in vias on the photosensitive polyimide layer, and planarization by chemical mechanical polishing (CMP), resulting in low production costs and an extremely flat surface that ensures void-free die bonding. A simultaneous metal/adhesive bonding process was also evaluated for high-throughput die-to-wafer bonding. Furthermore, the fine interconnect structure was verified to be fundamentally reliable.

System in wafer-level package technology with RDL-first process

We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication by using die-to-wafer (D2W) bonding with fine-pitch reflow soldering and simultaneous molding/underfilling at the wafer level.