Masayuki Uchida

Low-Stress Interconnection for Flip Chip BGA Employing Lead-Free Solder Bump

Flip chip bonding technology has been widely used for interconnection in high-end logic LSI employing lead-rich solder bumps. Recently, from an environmental issue, it is desired that the lead-rich solder should be replaced by lead-free solder. However, the stress at the interconnection after flip chip bonding reflow cannot be relaxed with lead-free solder bumps because of their poor creep properties. Since the stress causes delamination of the low-k layer under bumps and electrical open errors, the improvement of the solder bump material and the flip chip bonding process have been necessary for stress relaxation. In this study, we investigated the creep properties of Sn-0.7Cu and Sn-3.5Ag bumps by the indentation method. As a result, it was found that the creep properties of Sn-0.7Cu bumps was more suitable for stress relaxation than those of Sn-3.5Ag. Moreover, we confirmed that a low-stress interconnection had been achieved by employing Sn-0.7Cu bumps. The stress at the interconnection was less than the delaminating stress of the low-k layer. In addition, when the flip chip bonding was carried out by the reflow with the post-annealing, in which the temperature was held for a period of time at 200degC during reflow cooling part, the maximum stress in the low-k layer has been reduced by more than 36% in comparison with the low-k delaminating stress. Furthermore, it was found that the stresses at the flip chip joints were relaxed because of the increase of the creep rate which was caused by the reflow with the post-annealing.

Dilute Cu Alloying for Sn-Cu Bumping by Annealing Electroplated Cu/Sn Stacks on Ti/Ni/Pd UBM

Sn-Cu bumping has been demonstrated to employ sequential electroplating of Cu and Sn, followed by alloying the Cu/Sn stacks during reflow. Alloying behavior of the Cu/Sn stacks has been investigated with varying the underlying Cu thickness. The Cu6Sn5 based compounds were observed at the interface between a sputter deposited Ti/Ni/Pd under bump metallization and the Cu/Sn plated stack The underlying Cu was consumed by forming the intermetallic compounds as well as alloying with Sn, limiting the alloying Cu content in the Sn-Cu bump. With elevating reflow temperature, the alloying Cu content in the bump was slightly decreased. The result cannot be predicted by the solubility limit of Cu into Sn at a given reflow temperature based on the equilibrium phase diagram. The basic process design for the Cu/Sn stack has been provided. The intermetallic phase has been confirmed to work as a good diffusion barrier to Sn, leading to integrity of the Ni after solid state aging. The Cu/Sn stack plating process allows us to realize dilute Cu alloying with Sn for the eutectic composition and less Cu contents in the Sn-Cu bumps. In the bumping process, the thickness ratio of the Cu/Sn stack as plated does not need to be strictly controlled and a thick electrodeposited Ni layer is not necessary as the under bump metallization. This study confirms that electroplating provides a robust and cost-effective process for mass production of lead free bumping