Takashi Togasaki

Resin flow characteristics of underfill encapsulant for flip-chip interconnection

Flow characteristics of underfill encapsulant were evaluated to improve the flow of encapsulation resin into small gap between LSI chip and substrate so as to achieve uniform and void-free underfill encapsulant for high-reliability flip-chip interconnection. Encapsulant flow was observed through crystal TEG LSI chips using a video camera and its flow characteristics were evaluated using the Newtonian laminar flow model. The relationships between flow rate of underfill encapsulant and the bump stand-off height, the bump pitch and the bump gap of the adjoining bumps were obtained. The flow rate and flow distance were found to be functions of these bump design parameters. The bump design parameters for encapsulation to be perfectly complete and the maximum chip size permitting encapsulation were obtained from the results for high-reliability flip-chip interconnection. This paper describes the flow characteristics of underfill encapsulant that are necessary to achieve the uniform and void-free underfill encapsulant for LSI which has large chip size, small bump pitch and high I/O number.

Low-Stress Interconnection for Flip Chip BGA Employing Lead-Free Solder Bump

Flip chip bonding technology has been widely used for interconnection in high-end logic LSI employing lead-rich solder bumps. Recently, from an environmental issue, it is desired that the lead-rich solder should be replaced by lead-free solder. However, the stress at the interconnection after flip chip bonding reflow cannot be relaxed with lead-free solder bumps because of their poor creep properties. Since the stress causes delamination of the low-k layer under bumps and electrical open errors, the improvement of the solder bump material and the flip chip bonding process have been necessary for stress relaxation. In this study, we investigated the creep properties of Sn-0.7Cu and Sn-3.5Ag bumps by the indentation method. As a result, it was found that the creep properties of Sn-0.7Cu bumps was more suitable for stress relaxation than those of Sn-3.5Ag. Moreover, we confirmed that a low-stress interconnection had been achieved by employing Sn-0.7Cu bumps. The stress at the interconnection was less than the delaminating stress of the low-k layer. In addition, when the flip chip bonding was carried out by the reflow with the post-annealing, in which the temperature was held for a period of time at 200degC during reflow cooling part, the maximum stress in the low-k layer has been reduced by more than 36% in comparison with the low-k delaminating stress. Furthermore, it was found that the stresses at the flip chip joints were relaxed because of the increase of the creep rate which was caused by the reflow with the post-annealing.

High-density 3-D packaging technology based on the sidewall interconnection method and its application for CCD micro-camera visual inspection system

High-density three-dimensional (3-D) packaging technology for a charge coupled device (CCD) micro-camera visual inspection system module has been developed by applying high-density interconnection stacked unit modules. The stacked unit modules have fine-pitch flip-chip interconnections within Cu-column-based solder bumps and high-aspect-ratio Cu sidewall footprints for vertical interconnections. Cu-column-based solder bump design and underfill encapsulation resin characteristics were optimized to reduce the strain in the bump so as to achieve fine-pitch flip-chip interconnection with high-reliability. High-aspect-ratio Cu sidewall footprints were realized by the Cu-filled stacked vias at the edge of the substrate. High-precision distribution of sidewall footprints was achieved by laminating the multiple stacked unit substrates simultaneously. The fabricated high-density 3-D packaging module has operated satisfactorily as the CCD imaging data transmission circuit. The technology was confirmed to be effective for incorporating many large scale integrated (LSI) devices of different sizes at far higher packaging density than it is possible to attain using conventional technology. This paper describes the high-density 3-D packaging technology which enables all of the CCD imaging data transmission circuit devices to be packaged into the restricted space of the CCD micro-camera visual inspection system interior.

Dilute Cu Alloying for Sn-Cu Bumping by Annealing Electroplated Cu/Sn Stacks on Ti/Ni/Pd UBM

Sn-Cu bumping has been demonstrated to employ sequential electroplating of Cu and Sn, followed by alloying the Cu/Sn stacks during reflow. Alloying behavior of the Cu/Sn stacks has been investigated with varying the underlying Cu thickness. The Cu6Sn5 based compounds were observed at the interface between a sputter deposited Ti/Ni/Pd under bump metallization and the Cu/Sn plated stack The underlying Cu was consumed by forming the intermetallic compounds as well as alloying with Sn, limiting the alloying Cu content in the Sn-Cu bump. With elevating reflow temperature, the alloying Cu content in the bump was slightly decreased. The result cannot be predicted by the solubility limit of Cu into Sn at a given reflow temperature based on the equilibrium phase diagram. The basic process design for the Cu/Sn stack has been provided. The intermetallic phase has been confirmed to work as a good diffusion barrier to Sn, leading to integrity of the Ni after solid state aging. The Cu/Sn stack plating process allows us to realize dilute Cu alloying with Sn for the eutectic composition and less Cu contents in the Sn-Cu bumps. In the bumping process, the thickness ratio of the Cu/Sn stack as plated does not need to be strictly controlled and a thick electrodeposited Ni layer is not necessary as the under bump metallization. This study confirms that electroplating provides a robust and cost-effective process for mass production of lead free bumping

Process integration of fine pitch micro-bumping and Cu redistribution wiring for power efficient SiP

Leading-edge LSI products with 40nm logic technology node and beyond are facing the issue of how higher memory bandwidth is reconciled with lower power consumption. Chip stacking of a logic chip on a large-scale DRAM chip, interconnected with each other by fine-pitch bumps, provides a solution to realize a power efficient SiP (System in Package). In this paper, the successful process integration of 10µm pitch Cu redistribution wiring and 40µm pitch SnCu micro-bumping on 300mm wafers, together with chip-on-chip (CoC) joining, has been described in an effort to relinquish embedded DRAM (eDRAM) SoC (System on Chip).

Flip chip interconnects qualified for advanced low-k chips with SnCu bumps by alloying Cu/Sn plated stack

There are few reports of SnCu bumping by electroplating targeting on process qualification for an advanced low-k chips. In this study, the creep behavior of the SnCu solder alloy, fabricated by alloying a layered Cu/Sn plated stack, has been investigated in the actual feature size of flip chip interconnects in packages. The advantage of the SnCu bumps showing higher creep rates has led to reduction of chip package interaction. No reliability issues of the SnCu bumping with a pitch of 150 mum have been also confirmed for the 65 nm advanced low-k chips in flip chip interconnects. Integrity of the SnCu interconnects after thermal cycling has been discussed by the grain structures of the SnCu alloys.

High-density 3D packaging technology for CCD micro-camera system module

High-density three-dimensional (3D) packaging technology for a CCD micro-camera system module has been developed by applying high-density interconnection stack-unit modules that have fine-pitch flip-chip interconnections within copper-column-based solder bumps and high-aspect-ratio sidewall footprints for vertical interconnections. Copper-column-based solder bump design and underfill encapsulation resin characteristics were optimized to reduce the strain in the bump and to achieve fine-pitch flip-chip interconnection with high reliability. High-aspect-ratio sidewall footprints were realized by the copper-filled stacked vias at the edge of the module substrate. High-precision distribution of sidewall footprints was achieved by laminating the multiple stack-unit substrates simultaneously. The fabricated three-dimensional package has operated satisfactorily as the CCD imaging data transmission circuit module. The technology was confirmed to be effective for incorporating many devices of different sizes at far higher packaging density than it is possible to attain using conventional technology.

Ag plating and its impact on void-free Ag/Sn bumping

We have already developed the eutectic Sn-Ag solder bumping process by alloying Ag/Sn electroplated metal stacks to overcome some problems concerning Sn-Ag alloy plating. As the dimensions of solder bumps shrink, the effect of voids in the solder bumps on electromigration resistance must be discussed. For the Sn-Ag alloy plated bumps, voids in the solder bumps as reflow processed are difficult to be avoided. The large amount of degassed species from the alloy-plated bumps due to strong chemical agents trapped in the plated films has a close relation to generation of voids in the bumps. In contrast, though the stack plating process shows less degassing, micro-voids would be left at the interface of the plated stack as embryos of residual voids in the solder bumps. In this study, surface roughness of the underlying Ag films and degassing behavior of the Ag/Sn stack-plated bumps has been investigated using different types of Ag plating solutions. Gas analyses and X-ray imaging inspections were performed for the Ag/Sn plated stacks. Surface roughness of the underlying Ag layer was also characterized by a laser scanning and scanning electron microscopy. From the experimental results, it has been confirmed that less degassing is the most important issue for the Ag/Sn plated stacks. In addition, improvement of surface roughness of the underlying Ag plated films must not be neglected.