Matthew D. Moon

The effect of backside roughness on Al interconnect dimensions for RF CMOS SOI devices

Backside roughness variation on incoming Silicon-On-Insulator (SOI) wafers can cause systematic variations in the dimensions of Al interconnects. Wafers with more backside roughness are more effectively cooled during reactive ion etching (RIE), resulting in a lower wafer temperature during the etch, and a larger line width. The backside roughness of the SOI substrate must be considered in order to minimize wafer-to-wafer variations in the Al linewidth.

A process to reduce the occurrence of metal extrusions in al interconnects

Extrusions are a well-known phenomenon in Al interconnect stacks. We review experimental approaches to mitigate extrusions including depositing a low temperature oxide (LTO) on the film stack, modulation of the metal anneal conditions, and moving the anneal step from post-metal etch to post-metal deposition. After evaluation of the three potential solutions we determined that the movement of the anneal step from post-metal etch to post-metal deposition is the most manufacturable process.

The effect of etch residuals on via reliability

Vias are formed in interconnect structures using a polymerizing chemistry in order to avoid etching the underlying metal wires. However, a drawback of the polymerizing chemistry is that etch residues can remain in the via opening, resulting in high via resistance and possible degradation of circuit performance. Although it is well known that etch residues in vias can cause yield loss, the effect on reliability has not been reported for submicron vias. In this paper, the effect of etch residues on via reliability is studied. Vias with etch residues showed no degradation in reliability after a thermal cycle stress, high temperature storage, or humidity stress. However, vias with etch residues fail at a lower current during a wafer level voltage ramp electromigration stress, compared to residue-free vias, suggesting that etch residues will reduce the electromigration lifetime of interconnect structures.