Matthias Schöbinger

DSP-based signal processing for OFDM transmission

A demonstrator for orthogonal frequency division multiplex (OFDM) transmission based on a programmable DSP (TMS320C6201) is described. It turns out that the realized rather moderate sampling rates up to 10 Msamples/s still represent quite a challenge for state-of-the-art DSPs in terms of the required computational power but also the synchronization of the internal processing with the I/O interface to a real-time environment. It is illustrated that SW development under stringent resource constraints requires analysis and partitioning of the algorithms in a manner very similar to the mapping strategies necessary in an ASIC design for either cost-sensitive or extremely challenging applications. Therefore, the demonstrator development provides a sound basis for a subsequent design of such a kind of ASICs.

A low-cost point-to-multi-point access system based on OFDM transmission

A demonstrator for a cost-sensitive access system, with point-to-multi-point-transmission based on OFDM transmission in a shared medium is described. Time-domain-duplex (TDD), time-division multiple access (TDMA) and an efficient and robust synchronization algorithm have been implemented. The basic concepts are usable in radio links as well as in power-line communication systems.

Time-sharing architectures for FIR filter structures

Due to the still increasing gap between high clock rates which are technically feasible and essentially fixed sampling rates in many application domains time-sharing architectures are increasingly important. However, an efficient utilization of silicon resources cannot be achieved by a simple top-down approach for the mapping of sequential operations onto the same hardware. Rather the local topology of circuit design and layout has to be considered in order to maximize efficiency. Therefore modified bitplane architectures which provide exceptionally efficient silicon utilization due to the small synchronization overhead are used as a starting point. Several alternative time-sharing approaches have been elaborated in order to explore the possible choices for an adaptation to system requirements. A quantitative comparison for the most attractive architectures is provided which shows to what extent the advantages of modified bitplane architectures can be maintained. A typical example of a complex FIR filter serves as an illustration of the overhead of time-sharing architectures.

From Roadmaps to Reality: The Challenges of Designing Tomorrow's Chips

Ever smaller structures and ever greater numbers of semiconductor elements on a single chip call for a growing level of interdisciplinary creativity among chip and system developers. Also required are measures designed to significantly reduce the power dissipation associated with each function, even as clock rates accelerate. As integration increases, another requirement is to integrate combinations of analog and digital circuits on a single chip.