Thomas Nirschl

Yield and speed optimization of a latch-type voltage sense amplifier

A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.

Simulation of the Esaki-tunneling FET

Abstract As the dimension of the metal oxide semiconductor field effect transistor (MOSFET) keeping scaling, the short channel effects are becoming serious problems. Recently a MOS-based vertical tunneling transistor in silicon was proposed as a possible successor of the MOSFET. In this work, the device simulation of this novel transistor is performed in order to investigate the impacts of doping profile, gate oxide thickness and drain doping level on the device performance. The simulation shows that the sharp doping profile, thin gate oxide thickness and high drain doping level are the key technologies for fabricating the high performance Esaki-tunneling FET. Finally, the optimized device with high performance is proposed.

A yield-optimized latch-type SRAM sense amplifier

A yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It quantifies the impact of supply voltage, input dc level, transistor sizing and temperature on the input offset voltage. The input dc level turns out to be most significant. Also, an analytical expression for the sensing delay is derived. Experimental results in 130nm CMOS confirm that the yield can be significantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19mV to 8.5mV without affecting the delay which is measured to be 119ps at 1.5V supply.

The tunneling field effect transistor (TFET) used in a single-event-upset (SEU) insensitive 6 transistor SRAM cell in ultra-low voltage applications

This paper discusses the 6 transistor SRAM cell based on the complementary tunneling field effect transistors (TFET). The low voltage characteristics of the cell are presented. The static noise margin (SNM) is used to compare the TFET cell with the standard CMOS memory cell. Furthermore the sensitivity versus single-event-upset (SEU) caused by radiation is investigated.

Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits

Quasi adiabatic circuits like the efficient charge recovery logic (ECRL) are known to reduce dynamic power dissipation of digital CMOS circuits significantly. The possible operation frequencies have been continuously increased due to technology scaling. Anyway, the field of operation is limited to medium performance applications. If it was possible to operate a given adiabatic circuit also at extremely high frequencies there would be many new applications: A circuit working at a medium frequency most of the time and at high frequencies only for some burst mode operations could be implemented in adiabatic logic. This paper presents a new perspective of adiabatic circuits called adiabatic mode circuits. These circuits can be operated in a quasi adiabatic low-power mode but also in a high frequency domino mode if high speed data processing is required. Based on the 3-transistor DRAM cell a novel 3-transistor memory cell capable for adiabatic and conventional operation is presented. Thus new systems with a small total power consumption but temporarily high performance can be constructed.