Yeon-Ho Im

Fast development of source-level debugging system using hardware emulation

We describe the co-development of a processor and its source-level debugging system using an emulation-based validation technology including hardware emulation, not simulation, Since a source-level debugging system is essential to develop an application system and it takes a long time to validate the functionality of the source-level debugging system, we have adopted hardware emulation for a fast validation and system development. Using this methodology, we were able to validate the source-level debugging system successfully before the chip fabrication.

A method to generate soft shadows using a layered depth image and warping

We present an image-based method for propagating area light illumination through a Layered Depth Image (LDI) to generate soft shadows from opaque and nonrefractive transparent objects. In our approach, using the depth peeling technique, we render an LDI from a reference light sample on a planar light source. Light illumination of all pixels in an LDI is then determined for all the other sample points via warping, an image-based rendering technique, which approximates ray tracing in our method. We use an image-warping equation and McMillans warp ordering algorithm to find the intersections between rays and polygons and to find the order of intersections. Experiments for opaque and nonrefractive transparent objects are presented. Results indicate our approach generates soft shadows fast and effectively. Advantages and disadvantages of the proposed method are also discussed.

A hardware-like high-level language based environment for 3D graphics architecture exploration

The high complexity and the short lifetime of 3D graphics acceleration hardware increase the necessity of an environment for hardware development. For easy modification and fast testing of architecture, a high-level language based environment is desirable. Therefore, in this paper we propose a Graphics Architecture Testing Environment (GATE) that is based on Microsoft Visual C++. GATE models overall graphics hardware architecture through a modular approach, supports OpenGL, and offers easy modification and rapid testing of architecture. It also gathers computational statistics. A layered approach and Hardware Description Macro (HDM) support hardware modeling and architecture modification. Pre-defined types and operations provide statistical information. Several case studies of 3D graphics architecture on GATE show the capability of our environment.

Geometry engine architecture with early backface culling hardware

Most graphics accelerators waste valuable performance on transforming invisible vertices. To solve this problem, we have performed backface culling (BFC) earlier than transform and lighting (TnL). This paper proposes a survived vertex decision (SVD) algorithm to remove invisible vertices, and also suggests a geometry engine architecture that performs the early BFC with the SVD algorithm. This approach requires less hardware overhead. The SVD algorithm discards a vertex only if all triangles sharing that vertex are invisible in the mesh representing triangle lists or strips. The dedicated hardware performing the early BFC guarantees better performance in our approach, since it runs with the vertex engines in parallel. Particularly for a standalone engine, we introduce a unified architecture named the VP-Engine, which can perform the same tasks of the vertex engine and also handle the early BFC. Our architecture is designed using an instruction set simulator with a C++ library for cycle-accurate simulations. The early BFC removes half of the vertices that are transformed in the conventional approach, and as such the performance of our proposed architecture is twice as fast at maximum. Even with the sequential operations of early BFC and typical TnL, the VP-Engine is faster while the length of a vertex program is larger than 24.

FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit

This paper describes a VLIW (very long instruction word) geometry processor called FLOVA (FLOating-Point VLIW Architecture) which was developed to accelerate the geometry stage of 3D graphics. FLOVA executes four instructions in one cycle and supports 136 instructions including 35 SIMD (single instruction multiple data) instructions to accelerate the geometry stage. Special features to accelerate transformation and lighting operations in 3D graphics geometry stage are described. FLOVA can calculate the power value of two floating-point numbers in only four clock cycles with a negligible loss of accuracy, compared to over 150 clock cycles in other processors.

Co-development of media-processor and source-level debugger using hardware emulation-based validation

To exploit the development system with a media-processor as soon as possible, the co-development and co-validation of them is very important. We describe the co-development of a media-processor and its source-level debugger, which is necessary to develop multimedia systems. Even through a real chip is available, it takes a long time to validate the functionality of the source-level debugger. Here in this paper, we have adopted hardware emulation for a fast development and validation before a processor is fabricated.

DIVA: dual-issue VLIW architecture with media instructions for image processing

According to the demand on enormous multimedia data processing, we have designed a VLIW (very long instruction word) processor called DIVA (dual-issue VLIW architecture) exploiting the ILP (instruction-level parallelism) in multimedia programs. The DIVA processor which can execute two instructions in one cycle supports 86 instructions including 30 media instructions, and has a sub-word execution structure that supports the saturation mode arithmetic for image processing. Compared to scalar architectures without media instructions, the performance of the DIVA processor is improved by 2.2 to 5 times due to the combination of the VLIW architecture and media instructions. The DIVA processor, consisting of about 90,000 gates, was implemented using the 0.6 /spl mu/m CMOS SOG (sea-of-gate) process on a 8 mm/spl times/8 mm die, and has shown a performance of 80 MOPS (million operations per second) at 10 MHz clock frequency.

3D geometry graphics system using deferred primitive rendering with VLIW geometry processor

The geometry stage which performs the transformation and lighting operations of vertices, has become the critical part in the 3D graphics pipeline. We have designed the FGA (FLOVA Geometry Accelerator) that is the 3D geometry graphics system and it almost removes the time required for the process geometry stage. The 3D graphics library, FGA-GL, supports the FGA system. The deferred primitive rendering algorithm of FGA-GL enables the geometry processing of the primitive data to be done concurrently with the host job such as primitive data management or game AI. FGA improves the average performance of the 3D graphics system by 2.5-3.0 times.

Fast development of source-level debugging system using hardware emulation (short paper)

We describe the co-development of a processor and its source-level debugging system using an emulation-based validation technology including hardware emulation, not simulation, Since a source-level debugging system is essential to develop an application system and it takes a long time to validate the functionality of the source-level debugging system, we have adopted hardware emulation for a fast validation and system development. Using this methodology, we were able to validate the source-level debugging system successfully before the chip fabrication.

3D graphics system with VLIW processor for geometry acceleration

To process enormous 3D data, we have designed a VLIW (Very Long Instruction Word) processor called FLOVA (Floating-Point VLIW Architecture) exploiting the ILP (Instruction-Level Parallelism) in 3D programs. This paper presents FGA (FLOVA Geometry Accelerator) that is the 3D graphics system and it almost removes the time required to process in the geometry stage. We have developed the 3D graphics library, FGA-GL, to supports the FGA system. The deferred primitive rendering algorithm of FGA-GL enables the geometry processing of the primitive data to be done concurrently with the host job such as primitive data management or game play. FGA improves the average performance of 3D graphics system by 2.5-3.0.