Megan Snook

A Four-Terminal, Inline, Chalcogenide Phase-Change RF Switch Using an Independent Resistive Heater for Thermal Actuation

An inline chalcogenide phase-change radio-frequency (RF) switch using germanium telluride and driven by an integrated, electrically isolated thin-film heater for thermal actuation has been fabricated. A voltage pulse applied to the heater terminals was used to transition the phase-change material between the crystalline and amorphous states. An ON-state resistance of 4.5 Ω (0.08 Ω-mm) with an OFF-state capacitance and resistance of 35 fF and 0.5 MΩ, respectively, were measured resulting in an RF switch cutoff frequency (Fco) of 1.0 THz and an OFF/ON resistance ratio of 105. The output third-order intercept point measured , with zero power consumption during steady-state operation, making it a nonvolatile RF switch. To the best of our knowledge, this is the first reported implementation of an RF phase change switch in a four-terminal, inline configuration.

A 1680-V (at 1

A high-voltage normally ON 4H-SiC vertical junction field-effect transistor (VJFET) of 0.143- cm2 active area was manufactured in seven photolithographic levels with no epitaxial regrowth and with a single masked ion-implantation event. The VJFET exhibits low gate-to-source p-n-junction leakage current with relatively sharp onset of breakdown. At a drain-current density of 1 mA/cm2, the VJFET blocks 1680 V at a gate bias of -24 V. A self-aligned floating guard-ring structure provides edge termination that blocks 77% of the 11.8-mum SiC drift layers limit. At a gate bias of 2.5 V and a corresponding gate current of 2 mA, the VJFET outputs 53.6 A (375 A/cm2) at a forward drain voltage drop of 2.08 V (780 W/cm2). The transistor current gain is ID / IG = 26 800, and the specific on-state resistance is 5.5 mOmegamiddotcm2. To our best knowledge, this is the largest area SiC vertical-channel JFET reported to date and outputs more drain current than any 1200-V class vertical-channel JFET under identical heat-load and gate biasing conditions.

\hbox{mA/cm}^{2}

A normally on 4H-SiC vertical-junction field-effect transistor (VJFET) of 6.8-mm2 active area was manufactured in seven photolithographic levels with no epitaxial regrowth and a single masked ion-implantation event. The VJFET exhibits low leakage currents with very sharp onsets of voltage breakdowns. At a forward gate bias of 2.5 V, the VJFET outputs 24 A (353 A/cm2) at a forward drain-voltage drop of 2 V (706 W/cm2), with a current gain of ID/IG = 21818, and a specific ON-state resistance of 5.7 mOmegaldrcm2. Self-aligned floating guard rings provide edge termination that blocks 2055 V at a gate bias of -37 V and a drain-current density of 0.7 mA/cm2. This blocking voltage corresponds to 94.4% of the VJFETs 11.7-mum/3.46 times 1015-cm3 SiC drift layer limit and is the highest reported blocking-voltage efficiency of any SiC power device under similar drain-current-density conditions.

) 54-A (at 780

A normally-on 9-kV (at 0.1-mA/cm² drain leakage) 1.52 × 10^-3-cm² active-area vertical-channel SiC JFET (VJFET) is fabricated with no e-beam lithography, no epitaxial regrowth, and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped extension. The VJFET exhibits low leakage currents and a sharp onset of gate-voltage breakdown occurring at 80 V. To lower resistance, the VJFET is designed to be very normally-on, which minimizes the channel resistance contribution. At a gate bias of 0 V, the VJFETs drain current is 73 mA with a forward drain voltage drop of 5 V (240 W/cm²), a specific on-state resistance of 104 m ¿ · cm², and a current gain of I_D/I_G = 6.4 × 10⁶. Operating at a unipolar gate bias of 2.5 V lowers the on-state resistance to 96 m ¿ · cm² and raises the drain-current output to 79.3 mA, with the current gain being relatively high at I_D/I_G = 2346. Thus, this 9-kV VJFET is capable of efficient power switching operation with high current gain at a low unipolar resistance.

\hbox{W/cm}^{2}

SiC VJFETs are excellent candidates for reliable high-power/temperature switching as they only use pn junctions in the active device area where the high-electric fields occur. VJFETs do not suffer from forward voltage degradation, exhibit excellent short-circuit performance, and operate at 300°C. 0.19 cm2 1200 V normally-on and 0.15 cm2 low-voltage normally-off VJFETs were fabricated. The 1200-V VJFET outputs 53 A with a forward drain voltage drop of 2V and a specific onstate resistance of 5.4mΩcm2. The low-voltage VJFET outputs 28 A with a forward drain voltage drop of 3.3 V and a specific onstate resistance of 15mΩcm2. The 1200-V SiC VJFET was connected in the cascode configuration with two Si MOSFETs and with a low-voltage SiC VJFET to form normally-off power switches. At a forward drain voltage drop of 2.2V, the SiC/MOSFETs cascode switch outputs 33 A. The all-SiC cascode switch outputs 24 A at a voltage drop of 4.7 V.

) Normally ON 4H-SiC JFET With 0.143-

A recessed-implanted-gate (RIG) 1290-V normally-off (N-OFF) 4H-SiC vertical-channel JFET (VJFET), fabricated with a single masked ion implantation and no epitaxial regrowth, is evaluated for efficient power conditioning applications. The relationship between the VJFETs on-state resistance and current gain is elucidated. Under high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits a prohibitively high on-state resistance. Comparison with 1200-V normally-on VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V N-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high-current-gain VJFET operation. Perfecting the 1200-V edge termination structure, which can reduce the theoretical drift specific ON-state resistance from 2.2 to 1.5 mOmega ldr cm2, has a negligible impact in decreasing the channel-dominated 1200-V N-OFF VJFET resistance. The RIG VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial regrowth) revealed that, although aggressively increasing channel doping lowers the resistance, the corresponding reduction in the source mesa width can prohibitively limit manufacturability.

\hbox{cm}^{2}

A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.

Active Area

NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I_MAX>2.7 A/mm, V_PINCH = -8V, with R_ON=0.41 Ω-mm and C_OFF=0.19 pF/mm, for an RF switch FOM of F_CO=2.1 THz.

A 2055-V (at 0.7

Electron-hole recombination-induced stacking faults have been shown to degrade the I-V characteristics of SiC power p-n diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effect of bipolar gate-to-drain current on vertical-channel JFETs. The devices have n- drift epitaxial layers of 12-μm and 100-μm thicknesses, and were stressed at a fixed gate-to-drain current density of 100 A/cm2 for 500 hrs and 5 hrs, respectively. Significant gate-to-drain and on-state conduction current degradations were observed after stressing the 100-μm drift VJFET. Annealing at 350°C reverses the stress induced degradations. After 500 hours of stressing, the gate-to-source, gate-to-drain, and blocking voltage characteristics of the 12-μm VJFET remain unaffected. However, the on-state drain current was 79% of its pre-stress value. Annealing at 350°C has no impact on the post-stress on-state drain current of the 12-μm VJFET. This leads us to attribute the degradation to a “burn-in” effect.

\hbox{mA/cm}^{2}

High-voltage vertical-junction-field-effect-transistors (VJFETs) are typically designed normally-on to ensure low-resistance voltage-control operation at high current-gain. To exploit the high-voltage/temperature capabilities of VJFETs in a normally-off voltage-controlled switch, high-voltage normally-on and low-voltage normally-off VJFETs were connected in the cascode configuration. The cascode gate’s threshold voltage decreases from 2.5 V to 2 V as the temperature increases from 25°C to 225°C, while its breakdown voltage increases from -23 V to -19 V. At 300°C, the drain current of the cascode switch is 21.4% of its 25°C value, which agrees well with the reduction of the 4H-SiC electron mobility with temperature. The VJFET based all-SiC cascode switch is normally-off at 300°C, with its threshold voltage shifting from 1.6 V to 0.9 V as the temperature increases from 25°C to 300°C. This agrees well with the measured reduction in VJFET built-in potential. Finally, the reduction in cascode transconductance with temperature follows that of the theoretical 4H-SiC electron mobility. Overall, the measured thermally-induced cascode parameter shifts are in excellent agreement with theory, which signifies fabrication of robust SiC VJFETs for power switching applications.