Victor Veliadis

A Four-Terminal, Inline, Chalcogenide Phase-Change RF Switch Using an Independent Resistive Heater for Thermal Actuation

An inline chalcogenide phase-change radio-frequency (RF) switch using germanium telluride and driven by an integrated, electrically isolated thin-film heater for thermal actuation has been fabricated. A voltage pulse applied to the heater terminals was used to transition the phase-change material between the crystalline and amorphous states. An ON-state resistance of 4.5 Ω (0.08 Ω-mm) with an OFF-state capacitance and resistance of 35 fF and 0.5 MΩ, respectively, were measured resulting in an RF switch cutoff frequency (Fco) of 1.0 THz and an OFF/ON resistance ratio of 105. The output third-order intercept point measured , with zero power consumption during steady-state operation, making it a nonvolatile RF switch. To the best of our knowledge, this is the first reported implementation of an RF phase change switch in a four-terminal, inline configuration.

A 1680-V (at 1

A high-voltage normally ON 4H-SiC vertical junction field-effect transistor (VJFET) of 0.143- cm2 active area was manufactured in seven photolithographic levels with no epitaxial regrowth and with a single masked ion-implantation event. The VJFET exhibits low gate-to-source p-n-junction leakage current with relatively sharp onset of breakdown. At a drain-current density of 1 mA/cm2, the VJFET blocks 1680 V at a gate bias of -24 V. A self-aligned floating guard-ring structure provides edge termination that blocks 77% of the 11.8-mum SiC drift layers limit. At a gate bias of 2.5 V and a corresponding gate current of 2 mA, the VJFET outputs 53.6 A (375 A/cm2) at a forward drain voltage drop of 2.08 V (780 W/cm2). The transistor current gain is ID / IG = 26 800, and the specific on-state resistance is 5.5 mOmegamiddotcm2. To our best knowledge, this is the largest area SiC vertical-channel JFET reported to date and outputs more drain current than any 1200-V class vertical-channel JFET under identical heat-load and gate biasing conditions.

\hbox{mA/cm}^{2}

A normally on 4H-SiC vertical-junction field-effect transistor (VJFET) of 6.8-mm2 active area was manufactured in seven photolithographic levels with no epitaxial regrowth and a single masked ion-implantation event. The VJFET exhibits low leakage currents with very sharp onsets of voltage breakdowns. At a forward gate bias of 2.5 V, the VJFET outputs 24 A (353 A/cm2) at a forward drain-voltage drop of 2 V (706 W/cm2), with a current gain of ID/IG = 21818, and a specific ON-state resistance of 5.7 mOmegaldrcm2. Self-aligned floating guard rings provide edge termination that blocks 2055 V at a gate bias of -37 V and a drain-current density of 0.7 mA/cm2. This blocking voltage corresponds to 94.4% of the VJFETs 11.7-mum/3.46 times 1015-cm3 SiC drift layer limit and is the highest reported blocking-voltage efficiency of any SiC power device under similar drain-current-density conditions.

) 54-A (at 780

A normally-on 9-kV (at 0.1-mA/cm² drain leakage) 1.52 × 10^-3-cm² active-area vertical-channel SiC JFET (VJFET) is fabricated with no e-beam lithography, no epitaxial regrowth, and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped extension. The VJFET exhibits low leakage currents and a sharp onset of gate-voltage breakdown occurring at 80 V. To lower resistance, the VJFET is designed to be very normally-on, which minimizes the channel resistance contribution. At a gate bias of 0 V, the VJFETs drain current is 73 mA with a forward drain voltage drop of 5 V (240 W/cm²), a specific on-state resistance of 104 m ¿ · cm², and a current gain of I_D/I_G = 6.4 × 10⁶. Operating at a unipolar gate bias of 2.5 V lowers the on-state resistance to 96 m ¿ · cm² and raises the drain-current output to 79.3 mA, with the current gain being relatively high at I_D/I_G = 2346. Thus, this 9-kV VJFET is capable of efficient power switching operation with high current gain at a low unipolar resistance.

\hbox{W/cm}^{2}

A requirement for the commercialization of power SiC transistors is their long-term reliable operation under the hard-switching conditions encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state-circuit-breaker applications, were repetitively hard switched from a 150-V blocking state to an on-state current in excess of eight times the JFETs 250-W/cm2 rated current. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the p+ gates and guard rings and no epitaxial regrowth. The hard-switch testing was performed using an RLC circuit capable of currents in excess of 200 A with a rise time of 150 A/ μs. In this circuit, energy initially stored in the capacitor is discharged to the resistor through the JFET under test. The JFET hard-switch stressing included 1000 shots at each temperature of 25 °C, 50 °C, 100 °C, and 150 °C and at each repetition rate of 1, 5, 10, and 100 Hz for a total of 16 000 shots. Peak energies and powers dissipated by the JFET were 7.5 mJ and 9 kW, respectively. JFET conduction and blocking-voltage characteristics remain unchanged after 16 000 pulsed hard-switching events, which is indicative of reliable operation and excellent JFET suitability for nondegrading repeated bidirectional high surge-current fault isolation.

) Normally ON 4H-SiC JFET With 0.143-

SiC VJFETs are excellent candidates for reliable high-power/temperature switching as they only use pn junctions in the active device area where the high-electric fields occur. VJFETs do not suffer from forward voltage degradation, exhibit excellent short-circuit performance, and operate at 300°C. 0.19 cm2 1200 V normally-on and 0.15 cm2 low-voltage normally-off VJFETs were fabricated. The 1200-V VJFET outputs 53 A with a forward drain voltage drop of 2V and a specific onstate resistance of 5.4mΩcm2. The low-voltage VJFET outputs 28 A with a forward drain voltage drop of 3.3 V and a specific onstate resistance of 15mΩcm2. The 1200-V SiC VJFET was connected in the cascode configuration with two Si MOSFETs and with a low-voltage SiC VJFET to form normally-off power switches. At a forward drain voltage drop of 2.2V, the SiC/MOSFETs cascode switch outputs 33 A. The all-SiC cascode switch outputs 24 A at a voltage drop of 4.7 V.

\hbox{cm}^{2}

A requirement for the commercialization of power SiC transistors is their long-term reliable operation under hard switching conditions and high temperatures encountered in the field. Normally ON 1200-V vertical-channel implanted-gate SiC JFETs, designed for high-power bidirectional (four-quadrant) solid-state circuit breaker applications, were repetitively pulsed hard switched at 150°C from a 1200-V blocking state to an on-state current of 115 A, which is in excess of 13 times the JFETs 250-W/cm2 rated current at 150°C. The JFETs were fabricated in seven photolithographic levels with a single masked ion implantation forming the p+ gates and guard rings and with no epitaxial regrowth. The pulsed testing was performed using a low-inductance RLC circuit. In this circuit, the energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard switch stressing included over 2.4 million 1200-V/115-A hard switch events at 150°C and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 A/μs, and the pulse FWHM was 1.8 μs. After over 2.4 million hard switch events at 150°C, the JFET blocking voltage characteristics remained unchanged while the on-state current conduction slightly improved, which indicate reliable operation.

Active Area

A new normally-off 4H-silicon carbide (SiC) cascode circuit has been developed capable of offering current densities approaching 500 A/cm/sup 2/. The cascode circuit boasts a specific on-resistance of 3.6 m/spl Omega/cm/sup 2/ and over 1000 V blocking capability. A low-voltage, normally-off SiC JFET is used as the controlling device in series with a high-voltage normally-on SiC JFET capable of blocking over 1000 V. The SiC cascode circuit is shown operable at temperatures exceeding 150/spl deg/C. Silicon carbide cascode circuit switching speeds show comparable speeds to typical Si power MOSFETs in the same voltage range. Clamped inductive load switching measurements are performed to demonstrate the cascodes reverse bias safe operating area (RBSOA) capability. Switching characteristics of the integral power diode are also demonstrated.

A 2055-V (at 0.7

Bi-directional solid-state-circuit-breakers (SSCBs) are highly desirable in power-electronic fault-protection applications due to their high actuation speed and repeated fault isolation capability. Normally-on SiC vertical-channel JFETs (VJFETs) are excellent candidates for high power/temperature scalable SSCB applications as majority carrier devices with low conduction losses and stable +300°C thermal characteristics. 600-V / 2-A bi-directional power flow was demonstrated using two VJFETs connected back-to-back with their sources in common. The low VJFET pre-breakdown leakage currents and sharp onset of breakdown are critical in enabling bi-directional power flow. 0.1-cm2 low conduction-loss VJFETs were designed for efficient and reliable SSCB applications.

\hbox{mA/cm}^{2}

A recessed-implanted-gate (RIG) 1290-V normally-off (N-OFF) 4H-SiC vertical-channel JFET (VJFET), fabricated with a single masked ion implantation and no epitaxial regrowth, is evaluated for efficient power conditioning applications. The relationship between the VJFETs on-state resistance and current gain is elucidated. Under high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits a prohibitively high on-state resistance. Comparison with 1200-V normally-on VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V N-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high-current-gain VJFET operation. Perfecting the 1200-V edge termination structure, which can reduce the theoretical drift specific ON-state resistance from 2.2 to 1.5 mOmega ldr cm2, has a negligible impact in decreasing the channel-dominated 1200-V N-OFF VJFET resistance. The RIG VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial regrowth) revealed that, although aggressively increasing channel doping lowers the resistance, the corresponding reduction in the source mesa width can prohibitively limit manufacturability.