Mehdi Hamidi Sani

Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.

Low power embedded memory design – process to system level considerations

Embedded memories are widely used in low power System-on-Chip (SoC) applications. Low power performance can be optimized with process, circuits, architecture and system level co-development. In this paper, low power design considerations are described in advanced technology nodes to address memory leakage and active power dissipation. Memory bit cell design in context of process technology definition, circuit techniques at the macro design level, and chip-level integration considerations for low power are described.