Mehdi Salmani-Jelodar

Design Guidelines for Sub-12 nm Nanowire MOSFETs

Traditional thinking assumes that a light effective mass (m*), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light m* may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance (Cq). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum m* for sub-12-nm nanowire down to channel length of 3 nm. Optimum m* are found to range between 0.2-1.0 m0 and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. m* is no longer a material constant, but a geometry and strain dependent property of the channel material.

Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs

A widely used technique to mitigate gate leakage in ultrascaled metal oxide semiconductor field effect transistors ( mosfets) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as SiO2, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this paper, the effects of high-k oxides on double-gate (DG) mosfet with gate length under 20 nm are studied. All the devices are modeled using an effective mass quantum transport approach based on the quantum transmitting boundary method, where only ballistic transport is considered. We find that there is an optimum physical oxide thickness (TOX) to achieve the best performance in terms of on-current for each gate stack, including SiO2 interface layer and one high-k material. For the same EOT, Al2O3 (k = 9) over 3-Å SiO2 provides the best performance, while for HfO2 (k = 22) and La2O3 (k = 30), SiO2 thicknesses should be 5 Å and 7 Å, respectively. The effects of using high-k oxides and gate stacks on the performance of ultrascaled mosfets are analyzed. While thin oxide thickness increases the gate leakage, the thick oxide layer reduces the gate control on the channel. Therefore, the physical thicknesses of gate stack should be optimized to achieve the best performance.

Transistor roadmap projection using predictive full-band atomistic modeling

In this letter, a full band atomistic quantum transport tool is used to predict the performance of double gate metal-oxide-semiconductor field-effect transistors (MOSFETs) over the next 15 years for International Technology Roadmap for Semiconductors (ITRS). As MOSFET channel lengths scale below 20 nm, the number of atoms in the device cross-sections becomes finite. At this scale, quantum mechanical effects play an important role in determining the device characteristics. These quantum effects can be captured with the quantum transport tool. Critical results show the ON-current degradation as a result of geometry scaling, which is in contrast to previous ITRS compact model calculations. Geometric scaling has significant effects on the ON-current by increasing source-to-drain (S/D) tunneling and altering the electronic band structure. By shortening the device gate length from 20 nm to 5.1 nm, the ratio of S/D tunneling current to the overall subthreshold OFF-current increases from 18% to 98%. Despite this ON-current degradation by scaling, the intrinsic device speed is projected to increase at a rate of at least 8% per year as a result of the reduction of the quantum capacitance.

Contact modeling and analysis of InAs HEMT transistors

Novel device concepts and better channel materials than Si are required to improve the performance of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). The exploration of III–V semiconductors is mainly driven by the extremely high electron mobility of the materials. Recently, several researches have demonstrated that III–V high electron mobility transistors (HEMTs) can achieve high-speed operation at low supply voltage for applications beyond Si-CMOS technology. While the intrinsic device performance looks promising, current prototypes are dramatically influenced by high contact resistances. From a modeling point of view the understanding of the intrinsic device performance is now quite advanced, while the understanding of the contacts remains quite limited. Hence, a precise theoretical approach is required to model the contact characteristics. This work investigates the contact resistance physics of InAs HEMT transistors. The Nano-Electronic Modeling Tool (NEMO5) is used to solve the non-equilibrium Greens function (NEGF) formalism which embeds Schrödinger and Poisson equations self-consistently. For this study a real-space effective mass approximation with a simple phonon scattering is utilized.

Performance degradation due to thicker physical layer of high k oxide in ultra-scaled MOSFETs and mitigation through electrostatics design

In scaling the dimensions of transistors, gate oxide thicknesses are also scaled. Thinning SiO2 as gate oxide causes gate tunneling. In order to prevent the tunneling, high k dielectric have been used in place of SiO2. Using a thicker dielectric for the same equivalent oxide thickness (EOT) as SiO2 has a negative effect on the device performance through impacting 2D electrostatics. In this work, the effects of high k on double gate (DG) and silicon-on-insulator (SOI) devices are studied. It has been found that using high k for the same EOT can drastically drop the device performance for SOI and DG MOSFETs, with more pronounced degradation for SOI. Also, in thinning the channel thickness, the impact of oxide k variation can be reduced.

Model development for lattice properties of gallium arsenide using parallel genetic algorithm

In the last few years, evolutionary computing (EC) approaches have been successfully used for many real world optimization applications in scientific and engineering areas. One of these areas is computational nanoscience. Semi-empirical models with physics-based symmetries and properties can be developed by using EC to reproduce theoretically the experimental data. One of these semi-empirical models is the Valence Force Field (VFF) method for lattice properties. An accurate understanding of lattice properties provides a stepping stone for the investigation of thermal phenomena and has large impact in thermoelectricity and nano-scale electronic device design. The VFF method allows for the calculation of static properties like the elastic constants as well as dynamic properties like the sound velocity and the phonon dispersion. In this paper a parallel genetic algorithm (PGA) is employed to develop the optimal VFF model parameters for gallium arsenide (GaAs). This methodology can also be used for other semiconductors. The achieved results agree qualitatively and quantitatively with the experimental data.

Atomistic simulation of steep subthreshold slope Bi-layer MoS 2 transistors

The push for transistors with low standby power, marked by a sub-threshold swing (SS) less than 60mV/dec, has led to the investigation of exotic materials and novel mechanisms for FETs. Atomi-cally thin MoS2 has unique features which make it good candidate for future integrated circuits: having small body thickness and high mobility at the same time [1]. Bi-layer MoS2 is particularly interesting as its band gap can be tuned dynamically with an external field. This work investigates possible ways of lowering SS of the bi-layer MoS2 transistors such as using band-to-band-tunneling (BTBT) and dynamic band gap (DBG) tuning.

Quantum corrected drift-diffusion simulation for prediction of CMOS scaling

As the sizes of MOSFETs become smaller, the role of TCAD tools has increased significantly. Among TCAD tools, drift-diffusion (DD) simulators have been useful in providing insights into the operational principles of MOSFETs. DD simulators are fast due to a low computational burden compared to more sophisticated simulation methods such as full-band quantum transport simulators which cannot handle the volume of the bulk devices. However, as the device sizes become smaller, quantum mechanical (QM) effects render the DD results inaccurate. These QM phenomena are the ballistic resistance, the ballistic transport, the source-to-drain (SD) tunneling and the quantum confinement effects. In this work, these QM effects except the SD tunneling are dealt with such that DD tools can extend their use in modern nanoscale MOSFETs.