Miao Xu

Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate

In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. In combination with the structure advantage of conventional Si nanowires, the proposed S-FinFETs provide better electrostatic integrity in the channels than normal bulk-Si FinFETs or tri-gate devices with rectangular or trapezoidal fins. It is due to formation of quasi-surrounding gate electrodes on scalloping fins by a special Si etch process. The entire integration flow of the S-FinFETs is fully compatible with the mainstream all-last HKMG FinFET process, except for a modified fin etch process. The drain-induced barrier lowering and subthreshold swing of the fabricated p-type S-FinFETs with a 14-nm physical gate length are 62 mV/V and 75 mV/dec, respectively, which are much better than those of normal FinFETs with a similar process. With an improved short-channel-effect immunity in the channels due to structure modification, the novel structure provides one of possibilities to extend the FinFET scalability to sub-10-nm nodes with little additional process cost.

Improved Short Channel Effect Control in Bulk FinFETs With Vertical Implantation to Form Self-Aligned Halo and Punch-Through Stop Pocket

In this letter, for the first time, a novel vertical implantation is introduced in bulk FinFETs and used to form self-aligned halo and punch-through stop pocket (PTSP) at the same time. This implantation is carried out after dummy gate removal in the all-last high-k /metal gate process. The formed halo and PTSP doping profiles improve short channel effect control and reduce VTH variation. The process window related to the implantation is also discussed. This vertical implantation method is simple, effective, and has potential for future application of massive manufacture.

A Novel Fin Electron–Hole Bilayer Tunnel Field-Effect Transistor

A novel fin electron-hole bilayer tunnel field-effect transistor (FinEHBTFET) is proposed and investigated by simulation. In this structure, a narrow fin is placed at the middle of a conventional p+-i-n + tunnel field-effect transistor, and two separate gates formed on left and right sides of the fin are used to control the channel. The FinEHBTFET achieves drive current when band-to-band tunneling happens between the bias-induced electron-hole bilayer at the two sides of the fin. The FinEHBTFET shows a high Ion/Ioff ratio more than 106, and an average SS of 3 mV/dec over three decades of drain current.

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the devices scaling.

Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high-k (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF2 ion-implanted TiN/HfO2/ILSiO2 gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX

The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, V t -roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage ( V t ) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing V t at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.

Simulations of FDSOI CMOS with Sharing Contact between Source/Drain and Back Gate

In this paper, a new ultra-thin fully-depleted SOI CMOS structure with sharing contact between source/drain and back gate is presented to save area and increase threshold voltage tuning capability. TCAD simulations are used to investigate the back-gate effect on the ultra-thin SOI CMOS. A new process flow to make the fully-depleted SOI CMOS structures is also proposed.