Michael A. Shinosky

Line edge roughness and spacing effect on low-k TDDB characteristics

The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.

The Effect of Metal Area and Line Spacing on TDDB Characteristics of 45nm Low-k SiCOH Dielectrics

Low-k time-dependent dielectric breakdown (TDDB) is rapidly becoming one of the most important reliability issues in Cu/low-k technology development and qualification. Although considerable progress has been made in recent years in addressing the electric field dependence of low-k time-to-breakdown (tBD), there has been very little comprehensive work done on the effect of metal area and line spacing on low-k TDDB. The lifetime of a product chip is typically obtained by extrapolating TDDB data from small test structures to large chip areas, and the low-k TDDB line spacing scaling rule normally should be considered for the definition of operating voltages for various technologies to assure long-term reliability. Therefore, both area scaling and line spacing scaling relations are of great importance, in order to have a robust technology qualification. In this study, a thorough investigation into the 45 nm low-k SiCOH TDDB was conducted in order to understand the breakdown failure statistics, to model the area dependence, and to explore the line spacing scaling. With the help of experimental results and computational simulations, the effect of line-to-line spacing on low-k TDDB was clearly identified and a methodology for accurate determination of Weibull shape factor is proposed.

Critical ultra low-k TDDB reliability issues for advanced CMOS technologies

During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new “fatal” via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the “fatal” via ratio.

New breakdown data generation and analytics methodology to address BEOL and mol dielectric TDDB process development and technology qualification challenges

Both MOL PC-CA spacer dielectric and BEOL low-k dielectric breakdown data are commonly convoluted with multiple variables induced by process steps such as lithography, etch, CMP, cleaning, and thin film deposition. The traditional method of stressing one DUT per die or multiple DUTs per die, without careful data deconvolution, is incapable of addressing current complex MOL PC-CA and BEOL low-k dielectric breakdown modeling challenges. In this paper, a new big data generation method plus an analytics procedure method is proposed to soundly evaluate both MOL and BEOL dielectric time-dependent-dielectric breakdown data. A new diagnostic reliability concept is for the first time proposed for comprehensive process diagnostics and more accurate reliability failure rate determination.

Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues

The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as metal gate, epitaxial SiGe source /drain, stress liner, and copper contact together with new device configurations such as raised source/drain and FinFET may further exacerbate the PC-CA dielectric reliability. SRAM yield loss and functional stress failures of both SRAM and DRAM chips due to middle-of-line (MOL) PC-CA shorts and early breakdown have been observed during the course of technology development at 32nm. Therefore, the leakage and breakdown of middle-of-line (MOL) PC-to-CA dielectric is rapidly becoming an emerging reliability issue for a successful technology development. In this paper, a comprehensive investigation of MOL PC-to-CA reliability issues at 32nm technology node was conducted. A new qualification methodology was developed to assure PC-to-CA reliability at an acceptable level.

Invasion percolation model for abnormal time-dependent dielectric breakdown characteristic of low-k dielectrics due to massive metallic diffusion

With the continuing aggressive scaling of interconnect dimensions and introduction of lower k materials, back-end-of-line (BEOL) dielectric time-dependent dielectric breakdown (TDDB) reliability margin is greatly reduced. In this paper, a comprehensive investigation on abnormal low-k TDDB characteristics, a systematic degradation of Weibull slopes, and a systematic increase of field acceleration at lower stress voltages due to massive Cu diffusion were conducted for Cu interconnect with low-k dielectric. Based on data from extensive electrical and physical analysis, such abnormal TDDB characteristics were attributed to slow metallic diffusion in bulk low-k under bias and temperature stress. A TDDB model based on invasion percolation was proposed to model the observed abnormalities. Cu interconnects with robust liner and capping layer, to ensure metal free low-k film, have become important for BEOL low-k TDDB.

Soft breakdown characteristics of ultralow-k time-dependent dielectric breakdown for advanced complementary metal-oxide semiconductor technologies

During technology development, the study of ultralow-k (ULK) time-dependent dielectric breakdown (TDDB) is important for assuring robust reliability. As the technology advances, the increase in ULK leakage current noise level and reversible current change induced by soft breakdown (SBD) during stress has been observed. In this paper, the physical origin of SBD and reversible breakdown, and its correlation to conventional hard breakdowns (HBDs) were extensively studied. Based on constant voltage stress (CVS) and constant current stress (CCS) results, it was concluded that SBD in ULK is an intrinsic characteristic for ULK material, and all first breakdown events most likely are soft instead of hard. Therefore, a unified understanding of SBD and HBD for low-k TDDB was established. Furthermore, the post-SBD and HBD breakdown conduction characteristics were explored and their impacts on circuit operation were discussed. Based on current limited constant voltage stress studies, it was found that the power dissi...

Reliability Characterization of BEOL Vertical Natural Capacitor using Copper and Low-k SiCOH Dielectric for 65nm RF and Mixed-Signal Applications

Integration of low-cost and high performance passive capacitors into existing silicon CMOS technologies is essential for analog and radio frequency (RF) IC applications. Recently, BEOL vertical natural capacitors (VNCAP) with stacked via-comb structures have emerged as an attractive option due to their low-cost, high density, and highly symmetric configurations. In order to accurately predict low-k VNCAP reliability, in this study, both the time-dependent dielectric breakdown (TDDB) and capacitance stability (C-stability) of Cu/low-k SiCOH VNCAPs at 65nm technology node were thoroughly investigated. The TDDB performance of Cu/SiCOH VNCAP was found to be sensitive to device layouts and process. Capacitance stability was found to be sensitive to the presence of moisture in SiCOH low-k film during process. With the optimal device design and process, SiCOH VNCAP was found to exhibit robust TDDB performance, as well as absence of capacitance instability during high temperature stress (HTS)

Electron fluence driven, Cu catalyzed, interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

Abstract During technology development, the study of low- k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low- k TDDB are closely correlated with the leakage conduction mechanism of low- k dielectrics. In addition, low- k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low- k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low- k breakdown model. Then we review several other low- k TDDB models that consider only intrinsic low- k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low- k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low- k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low- k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.

Extreme-Value Statistics and Poisson Area Scaling With a Fatal-Area Ratio for Low-

During the study of time-dependent dielectric breakdown (TDDB) of back-end-of-line low- k dielectrics, accurate statistical and area-scaling models are important for the final reliability lifetime projection. The extrapolated product lifetime from high percentiles to low percentiles has strong dependence on the choice of a statistical model. Meanwhile, the lifetime of a product chip is obtained typically by extrapolating TDDB data from small test structures to large chip areas by an area-scaling law. In this paper, a thorough investigation of low-k TDDB statistical distribution with large sample size and various metal areas was conducted to validate a physically relevant statistical model for low-k TDDB modeling. In addition, we explored the various TDDB dependence on metal area and introduced a new fatal-area-ratio concept for low-k TDDB area-scaling model in the event that the conventional Poisson area-scaling law failed based on the as-designed area ratio. A graphic shift-and-compare method was then developed to determine, experimentally, the fatal-metal-area ratio. The determination of the fatal-metal-area ratio should be critical for an accurate low-k TDDB lifetime projection and process assessment.