John M. Aitken

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFETs is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 1010cm-2) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm2. Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 1010cm-2.

Critical ultra low-k TDDB reliability issues for advanced CMOS technologies

During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new “fatal” via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the “fatal” via ratio.

Current and C‐V instabilities in SiO2 at high fields

Results have been obtained concerning the interrelation of current and C‐V instabilities in MOS capacitors subjected to negative gate high‐field pulsing. Rising current transients and negative C‐V shifts both show the formation of positive charge in the oxide. However, this charge appears to be situated close to the electrodes rather than in the bulk of the oxide and the temperature dependence of the rate of charge accumulation near the electrodes is different for the aluminum and silicon electrodes. These results indicate that the current instabilities and C‐V shifts appear to result from independent mechanisms.

Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues

The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as metal gate, epitaxial SiGe source /drain, stress liner, and copper contact together with new device configurations such as raised source/drain and FinFET may further exacerbate the PC-CA dielectric reliability. SRAM yield loss and functional stress failures of both SRAM and DRAM chips due to middle-of-line (MOL) PC-CA shorts and early breakdown have been observed during the course of technology development at 32nm. Therefore, the leakage and breakdown of middle-of-line (MOL) PC-to-CA dielectric is rapidly becoming an emerging reliability issue for a successful technology development. In this paper, a comprehensive investigation of MOL PC-to-CA reliability issues at 32nm technology node was conducted. A new qualification methodology was developed to assure PC-to-CA reliability at an acceptable level.

Invasion percolation model for abnormal time-dependent dielectric breakdown characteristic of low-k dielectrics due to massive metallic diffusion

With the continuing aggressive scaling of interconnect dimensions and introduction of lower k materials, back-end-of-line (BEOL) dielectric time-dependent dielectric breakdown (TDDB) reliability margin is greatly reduced. In this paper, a comprehensive investigation on abnormal low-k TDDB characteristics, a systematic degradation of Weibull slopes, and a systematic increase of field acceleration at lower stress voltages due to massive Cu diffusion were conducted for Cu interconnect with low-k dielectric. Based on data from extensive electrical and physical analysis, such abnormal TDDB characteristics were attributed to slow metallic diffusion in bulk low-k under bias and temperature stress. A TDDB model based on invasion percolation was proposed to model the observed abnormalities. Cu interconnects with robust liner and capping layer, to ensure metal free low-k film, have become important for BEOL low-k TDDB.

A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS

A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments employing both AC and DC stress/relax BTI measurements are undertaken to characterize FETs threshold voltage instability response to a dynamic (inverter type) operation. Results from the AC stress experiments demonstrate that VT instability is frequency independent, an observation that suggests that VT degradation under AC stress can be equivalently measured through the simpler DC stress/relax sequence. An AC BTI model is developed that accurately captures the critical BTI relaxation effect through the DC stress/relax predictions on duty cycle dependence. A Ring Oscillator (RO) circuit is used as a model verification vehicle. Excellent agreement is demonstrated between the frequency degradation measurements obtained with a newly developed Ultra-Fast On-The-Fly (OTF) measurement technique optimized for BTI and the AC BTI model based RO simulations.

Extreme-Value Statistics and Poisson Area Scaling With a Fatal-Area Ratio for Low-

During the study of time-dependent dielectric breakdown (TDDB) of back-end-of-line low- k dielectrics, accurate statistical and area-scaling models are important for the final reliability lifetime projection. The extrapolated product lifetime from high percentiles to low percentiles has strong dependence on the choice of a statistical model. Meanwhile, the lifetime of a product chip is obtained typically by extrapolating TDDB data from small test structures to large chip areas by an area-scaling law. In this paper, a thorough investigation of low-k TDDB statistical distribution with large sample size and various metal areas was conducted to validate a physically relevant statistical model for low-k TDDB modeling. In addition, we explored the various TDDB dependence on metal area and introduced a new fatal-area-ratio concept for low-k TDDB area-scaling model in the event that the conventional Poisson area-scaling law failed based on the as-designed area ratio. A graphic shift-and-compare method was then developed to determine, experimentally, the fatal-metal-area ratio. The determination of the fatal-metal-area ratio should be critical for an accurate low-k TDDB lifetime projection and process assessment.

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Junction breakdown voltage instability in a p-n junction formed in bulk silicon adjacent to a deep trench filled with polysilicon was investigated. The structure investigated consists of a 5- mu m-deep trench filled with heavily p-doped polysilicon. The trench is open at the bottom and is consequently shorted to the p-substrate. The time-dependent behavior of the walkout or the breakdown voltage instability is similar to that reported for planar p-n junctions terminating on surface oxide. Results suggest that trapping of holes in the trench sidewall dielectric is responsible for this phenomenon. The product of trapping center concentration and capture cross section N sigma is estimated to be 90 cm/sup -1/. >

Dielectric TDDB Modeling

Both MOL PC-CA spacer dielectric and BEOL low-k dielectric breakdown data are commonly convoluted with multiple variables present in the data due to the involvement of many process steps such as lithography, etch, CMP, cleaning, and thin film deposition. With the continuing aggressive scaling of device dimensions and introduction of new device configurations, how to accurately analyze such complicated lateral dielectric breakdown data from MOL and BEOL TDDB in advanced VLSI circuits has become very challenging. In this paper, a new electrical method is developed to accurately characterize different variables in MOL and BEOL dielectric breakdown. This method provides a powerful way to do a fast deep dive process and reliability analysis for technology development and qualification without time consuming physical failure analysis.

Junction breakdown instabilities in deep trench isolation structures

Low-k time dependent dielectric breakdown (TDDB) is commonly considered an important reliability issue. It has been proposed that there is an interrelation of field and temperature dependence between TDDB thermal activation energies and field acceleration parameters, which could provide a more comprehensive picture to understand low-k TDDB breakdown mechanism. In this study, an extensive investigation of low-k TDDB degradation at 32nm over a wide range of fields and temperatures was conducted for Cu interconnects with and without regular TaN/Ta liner. New interrelations of field and temperature dependence between TDDB thermal activation energies and field acceleration parameters for Cu samples with and without liner were experimentally identified, which provide a new insight to roles of Cu in low-k TDDB breakdown model.