Michael Bajura

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Qcrit) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.

A modular power-aware microsensor with >1000X dynamic power range

We introduce a power-aware microsensor architecture supporting a wide operational power range (from <1 mW to >10 W). The platform consists of a family of modules that follow a common set of design principles. Each module includes a local power microcontroller, power switches, and isolation switches to enable independent power-down control of modules and module subsystems. Processing resources are scaled appropriately on each module for their role in the collective system. Hard real-time functions are migrated to the sensor and radio modules for improved power efficiency. The optional Linux-based processor module supports high duty cycling and advanced sleep modes. Our reference hardware implementation is described in detail in this paper. Seven different modules have been developed. We utilize an acoustic vehicle tracking application to demonstrate how the architecture operates and report on results from field tests on tracked and wheeled vehicles.

Split-fabrication obfuscation: Metrics and techniques

Split-fabrication has been proposed as an approach for secure and trusted access to advanced microelectronics manufacturing capability using un-trusted sources. Each wafer to be manufactured is processed by two semiconductor foundries, combining the front-end capabilities of an advanced but untrusted semiconductor foundry with the back-end capabilities a trusted semiconductor foundry. Since the security of split fabrication relates directly to a front-end foundrys ability to interpret the partial circuit designs it receives, metrics are needed to evaluate the obfuscation of these designs as well as circuit design techniques to alter these metrics. This paper quantitatively examines several “front-end” obfuscation techniques and metrics inspired by information theory, and evaluates their impact on design effort, area, and performance penalties.

Cross-Layer Modeling and Simulation of Circuit Reliability

Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the degradation rate. To improve design predictability and guarantee system lifetime, accurate modeling, and simulation tools for reliability are essential to both digital and analog circuits. This paper presents cross-layer solutions for emerging reliability threats, including: 1) device-level modeling of reliability mechanisms, such as transistor aging and its statistical behavior; 2) circuit-level long-term aging models that capture unique operation patterns in digital and analog design, and directly predict the degradation; and 3) simulation methods for very-large-scale designs. Built on the long-term model, the new methods significantly enhance the accuracy and efficiency of reliability analysis. As validated by silicon data, these solutions close the gap between the underlying reliability physics and circuit/system design for resilience.

Power-aware microsensor design

Military microsensors are networked distributed embedded systems composed of a processor, a radio, and sensors used for personnel or vehicle detection. They are most often found in minefield replacement and perimeter security applications where size, weight, power, and cost requirements are quite challenging. In this paper, we discuss the different system design approaches used in microsensor systems and introduce a modular, scalable, power-aware microsensor architecture intended span the entire dynamic range required of these systems. We describe a reference implementation of this concept and results from field experiments.

An integrated modular power-aware microsensor architecture and application to unattended acoustic vehicle tracking

We introduce a truly modular, power-aware, distributed microsensor architecture, capable of seamlessly spanning performance metrics from point-optimized low-power to point-optimized high-power applications. This type of performance is often needed in unattended ground sensor applications such as acoustic sensing and tracking, where long periods of minimal sensing activity are intermixed with short periods of intense sensor processing. The system design and implementation of a microsensor platform based on this architecture are described with experimental results. We show that although building a modular power-aware system requires additional hardware components, it results in system capable of rapid physical hardware and software reconfiguration with module reuse for new applications, while achieving a significant decrease in overall system power.

Dual threshold voltage adder for robust sub-Vt operation in 65nm technology

With the increased focus on power efficiency, there is a push towards lowering the supply voltage and operating the design in the sub-threshold regime. While this is good for lowering the active power, it makes certain circuits more susceptible to single-event effects due to poor Ioff/Ion ratio. The 28-T mirror adder is a key building block for many arithmetic and digital signal processing systems. Yet, the mirror full adder is vulnerable to failure in sub-threshold operation due to its long chain of transistors in series and xor-parallel configuration. By replacing the transistors in the vulnerable configuration with low-Vt transistors, we are able to strengthen the circuit for sub-threshold operation. In this paper, we look at the effect of a dual-Vt version of the basic mirror adder circuit in the 65nm technology node.