L.C. Riewe

Effects of oxide traps, interface traps, and ‘‘border traps’’ on metal‐oxide‐semiconductor devices

We have identified several features of the 1/f noise and radiation response of metal‐oxide‐semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ‘‘oxide traps’’ are simply defects in the SiO2 layer of the MOS structure, and ‘‘interface traps’’ are defects at the Si/SiO2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ‘‘fixed states’’ are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ‘‘switching states’’ can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface tr...

An improved standard total dose test for CMOS space electronics

The postirradiation response of hardened and commercial CMOS devices is investigated as a function of total dose, dose rate, and annealing time and temperature. Cobalt-60 irradiation at approximately=200 rad(SiO/sub 2/)/s followed by a one-week 100 degrees C biased anneal and testing is shown to be an effective screen of hardened devices for space use. However, a similar screen and single-point test performed after Co-60 irradiation and elevated-temperature anneal cannot be generally defined for commercial devices. In the absence of detailed knowledge about device and circuit radiation response, a two-point standard test is proposed to ensure space survivability of CMOS circuits; a Co-60 irradiation and test to screen against oxide-trapped-charge-related failures, and an additional rebound test to screen against interface-trap-related failures. Testing implications for bipolar technologies are also discussed. >

Latent interface-trap buildup and its implications for hardness assurance (MOS transistors)

Long-term anneals at temperatures from 25 degrees C to 135 degrees C were performed on irradiated MOS transistors. Following the normal saturation of interface-trap density (within 10/sup 2/ to 10/sup 5/ s after irradiation), large increases in the number of interface traps were observed for both commercial and radiation-hardened transistors at very long times after irradiation (>10/sup 6/ s at 25 degrees ). This latent buildup of interface traps can be significant, up to a factor of four times larger than the normal saturation value. The latent buildup is thermally activated with an activation energy of 0.47+or-0.08 eV. As a natural consequence of the delay between the normal and the latent buildup, there is a window in time in which little or no interface-trap buildup occurs. Two possible mechanisms for the latent buildup are explored: (1) the direct conversion of oxide traps into interface traps or border traps and (2) the diffusion of molecular hydrogen into the gate oxide from adjacent structures. The latent buildup of interface traps can degrade the performance of ICs in space systems and may cause IC failure at long times. Recommendations are provided for characterizing latent interface-trap buildup. >

Thermal-stress effects and enhanced low dose rate sensitivity in linear bipolar ICs

A pre-irradiation elevated-temperature stress is shown to have a significant impact on the radiation response of a linear bipolar circuit. Thermal cycling can lead to part-to-part variability in the radiation response of circuits packaged from the same wafer. In addition, it is demonstrated that a pre-irradiation elevated-temperature stress can significantly impact the enhanced low dose rate sensitivity (ELDRS) of the LM111 voltage comparator. Thermal stress moderates and, in some cases, eliminates ELDRS. The data are consistent with space charge models. These results suggest that there may be a connection between the mechanisms responsible for thermal-stress effects and ELDRS in linear circuits. Implications of these results for hardness assurance testing and mechanisms are discussed.

The role of border traps in MOS high-temperature postirradiation annealing response

A very-long-term study of the response of nonradiation-hardened MOS transistors to elevated-temperature, postirradiation biased anneals has been performed. The midgap-voltage shift of these devices returns to approximately 0 V during a 2.75-year, +6 V 100 degrees C anneal, supporting the idea that in these devices interface traps and border traps (near-interfacial oxide traps which can exchange charge with the underlying Si) are charge-neutral at midgap. Subsequent switched-bias annealing reveals that a significant fraction of the radiation-induced trapped holes have not been removed from the device, but are compensated by electrons in border traps. These border traps can lead to large, reversible changes in midgap-voltage shifts and/or subthreshold stretchout during switched-bias anneals. Midgap-voltage and subthreshold-stretchout reversibility remains significant in these devices even after annealing at temperatures up to 350 degrees C. Similar reversibility in postirradiation response is observed for hardened transistors and capacitors. These results suggest that border traps may lead to increased reliability problems in some irradiated devices as compared to their unirradiated counterparts. >

Impact of passivation layers on enhanced low-dose-rate sensitivity and pre-irradiation elevated-temperature stress effects in bipolar linear ICs

Final chip passivation layers are shown to have a major impact on the total dose hardness of bipolar linear technologies. It is found that devices fabricated without passivation layers do not exhibit enhanced low-dose-rate sensitivity (ELDRS) or pre-irradiation elevated-temperature stress (PETS) sensitivity, whereas devices from the same production lot fabricated with either oxide/nitride or doped-glass passivation layers are ELDRS and PETS sensitive. In addition, removing the passivation layers after fabrication can mitigate ELDRS and PETS effects. ELDRS and PETS effects do not appear to be inherently related to circuit design or layout, but are related to mechanical stress effects, hydrogen in the device, or a combination of the two. These results suggest that proper engineering of the final chip passivation layer might eliminate ELDRS and PETS effects in bipolar integrated circuits.

1/f noise in n- and p-channel MOS devices through irradiation and annealing

The 1/f noise of n- and p-channel MOS transistors was investigated through irradiation and biased anneals. While the increase in noise during irradiation is similar for both types of devices, the noise differs significantly in response to biased anneals. In particular, the noise decreases with decreasing Delta V/sub ot/ during positive-bias anneals in nMOS transistors but increases during positive-bias anneals for pMOS transistors. Conversely, negative bias anneals increase the noise in nMOS devices but decrease the noise in pMOS devices. These results are explained in terms of majority carrier trapping and detrapping at oxide defects near the Si/SiO/sub 2/ interface. Under normal operating bias conditions (positive bias for nMOS and negative bias for pMOS), the 1/f noise of both n- and p-channel transistors decreases through postirradiation annealing. >

Predicting switched-bias response from steady-state irradiations MOS transistors

A novel semiempirical model of radiation-induced charge neutralization is presented. This model is combined with 12 heuristic guidelines derived from studies of oxide- and interface-trap charge ( Delta V/sub ot/ and Delta V/sub it/) buildup and annealing to develop a method to predict MOS switched-bias response from steady-state irradiations, with no free parameters. For n-channel MOS devices, predictions of Delta V/sub ot/, Delta V/sub it/, and mobility degradation differ from experimental values through irradiation by less than 30% in all cases considered. This is demonstrated for gate oxides with widely varying Delta V/sub ot/ and Delta V/sub it/ and for parasitic field oxides. Preliminary results suggest that n-channel MOS Delta V/sub ot/ annealing and Delta V/sub it/ buildup following switched-bias irradiation and through switched-bias annealing also may be predicted with less than 30% error. The p-channel MOS response at high frequencies (>1 kHz) is more difficult to predict. >

Correlation between Co-60 and X-ray radiation-induced charge buildup in silicon-on-insulator buried oxides

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

BULK OXIDE TRAPS AND BORDER TRAPS IN METAL-OXIDE-SEMICONDUCTOR CAPACITORS

Thermally stimulated current (TSC) and capacitance–voltage measurements are combined via a newly developed analysis technique to estimate positive and negative oxide-trap charge densities for metal–oxide–semiconductor (MOS) capacitors exposed to ionizing radiation or subjected to high-field stress. Significantly greater hole trapping than electron trapping is observed in 3% borosilicate glass (BSG) insulators. Two prominent TSC peaks are observed in these BSG films. A high-temperature peak near 250 °C is attributed to the Eγ′ defect, which is a trivalent Si center in SiO2 associated with an O vacancy. A lower temperature positive charge center near 100 °C in these films is likely to be impurity related. The higher temperature Eγ′ peak is also observed in 10, 17, and 98 nm thermal oxides. A much weaker secondary peak is observed near ∼60 °C in some devices, which likely is due to metastably trapped holes in the bulk of the SiO2. Negative charge densities in these thermal oxides are primarily associated wit...