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Dive into the research topics where Michael Francis Chisholm is active.

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Featured researches published by Michael Francis Chisholm.


Microelectronics Technology and Process Integration | 1994

Chemical mechanical planarization of multilayer dielectric stacks

Manoj K. Jain; Girish A. Dixit; Michael Francis Chisholm; Thomas R. Seha; Kelly J. Taylor; Gregory B. Shinn; Robert H. Havemann

Sub-0.5 micrometers multilevel metal schemes impose stringent requirements on both gap-fill and planarity of interlevel dielectrics. A variety of novel materials and processes are being investigated to meet these process requirements. In this paper, four dielectrics with good gap- filling capabilities are evaluated for planarity characteristics: SiO2 deposited using a high density plasma (HDP) with simultaneous deposition and sputtering, an organic spin-on-glass material SOG-A, an inorganic spin-on-glass material SOG-B, and SiO2 deposited using ozone and TEOS at sub-atmospheric pressure (SACVD). These materials are used for gap-fill followed by a capping layer of PETEOS. For global planarization, only the top layer of PETEOS is planarized using chemical mechanical polishing (CMP) without exposing the underlying gap-fill material. Planarization characteristics of the dielectric stacks are found to be significantly different, both before and after CMP. The CMP throughput is found to be very sensitive to the choice of the dielectric stack. For a given planarity goal, the CMP throughputs of three of the dielectric stacks are found to be significantly higher than that of a conventional single layer interlevel dielectric (ILD) consisting of only PETEOS.


Microelectronics Technology and Process Integration | 1994

Chemical Vapor deposition (CVD) TiN: a barrier metallization for submicron via and contact applications

Karl A. Littau; Rod Mosely; M. Eizenberg; Hung V. Tran; Ashok K. Sinha; Girish A. Dixit; Manoj K. Jain; Michael Francis Chisholm; Robert H. Havemann

A new technique for low temperature CVD TiN is introduced as a barrier/glue layer for sub 0.5 micron applications. Excellent conformity (> 70%) is achieved while maintaining good electrical performance and reliability. The films are shown to be polycrystalline TiN with no preferred grain orientation. In addition compositional analysis shows significant amounts of carbon in the film presumably between the grains. The electrical properties of the CVD film were evaluated at the via and contact level. The contact and via resistances of tungsten plugs using CVD TiN glue layers are shown to be comparable to plugs using sputtered TiN. The barrier performance of the film was also evaluated at the contact level. The superior junction leakage data indicate that the CVD TiN film should have wide application as a barrier metal for sub 0.5 mm applications.


Archive | 1994

Semiconductor substrate conditioning head having a plurality of geometries formed in a surface thereof for pad conditioning during chemical-mechanical polish

Andrew T. Appel; Michael Francis Chisholm


Archive | 1994

Compact system and method for chemical-mechanical polishing utilizing energy coupled to the polishing pad/water interface

Michael Francis Chisholm; Andrew T. Appel


Archive | 1995

Conductor reticulation for improved device planarity

Manoj K. Jain; Michael Francis Chisholm


Archive | 1996

Apparatus integrating pad conditioner with a wafer carrier for chemical-mechanical polishing applications

Andrew T. Appel; Michael Francis Chisholm


Archive | 1996

Selective CMP of in-situ deposited multilayer films to enhance nonplanar step height reduction

Michael Francis Chisholm


Archive | 1995

Application of semiconductor IC fabrication techniques to the manufacturing of a conditioning head for pad conditioning during chemical-mechanical polish

Andrew T. Appel; Michael Francis Chisholm


Archive | 1995

Improved device planarity

Manoj K. Jain; Michael Francis Chisholm


Archive | 1996

Improvements in or relating to semiconductor wafer fabrication

Andrew T. Appel; Michael Francis Chisholm

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