Abhitosh Vais

Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures

Abstract In this work, we have systematically studied the frequency dispersion of the capacitance–voltage (C–V) characteristics of In0.53Ga0.47As metal–oxide-semiconductor (MOS) capacitors in accumulation region at various temperatures based on a distributed border traps model. An empirical method to evaluate the frequency and temperature dependent response of the border traps distributed along the depth from the interface into the oxide is established. While the frequency dependent response results from the dependence of the time constant of the border traps on their depths, the temperature dependent response is ascribed to the thermal activated capture cross-section of the border traps due to the phonon-related inelastic capturing process. Consequently, it is revealed that the frequency dispersion behaviors of the accumulation capacitance at different temperatures actually reflect the spatial distribution of the border traps. On this basis, we propose a methodology to extract the border trap distribution in energy and space with emphasis on analyzing the C–V characteristics measured from low to high temperatures in sequence.

Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps

This paper presents a detailed investigation of the temperature dependence of frequency dispersion observed in capacitance-voltage (C-V) measurements of III-V metal-oxide-semiconductor (MOS) devices. The dispersion in the accumulation region of the capacitance data is found to change from 4%–9% (per decade frequency) to ∼0% when the temperature is reduced from 300 K to 4 K in a wide range of MOS capacitors with different gate dielectrics and III-V substrates. We show that such significant temperature dependence of C-V frequency dispersion cannot be due to the temperature dependence of channel electrostatics, i.e., carrier density and surface potential. We also show that the temperature dependence of frequency dispersion, and hence, the capture/emission process of border traps can be modeled by a combination of tunneling and a “temperature-activated” process described by a non-radiative multi-phonon model, instead of a widely believed single-step elastic tunneling process.

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

Impact of starting measurement voltage relative to flat-band voltage position on the capacitance-voltage hysteresis and on the defect characterization of InGaAs/high-k metal-oxide-semiconductor stacks

In this work, we discuss how the position of the flat band voltage with respect to the starting voltage of the C-V measurement sweep can influence the estimation of the hysteresis in high-k/InGaAs MOS devices. We show that, with the support of experimental data and conceptual oxide defect band calculations, the interpretation and subsequent parameter extraction from flat-band voltage shifts observed in III-V MOS devices is more complex as compared to Si gate stacks. It is demonstrated that such complication arises due to the wider distribution of defect levels in the dielectric band gap in the case of InGaAs/high-k stack as compared to standard Si/SiO2/HfO2 MOS. In particular, for Al2O3 deposited on InGaAs, two wide, partially overlapping oxide defect bands are identified, centered ∼1.5 eV and ∼0.5 eV above and below the channel conduction band, respectively. Such defect levels are expected to affect the device operation and reliability.

A Unified Two-Band Model for Oxide Traps and Interface States in MOS Capacitors

The distributed oxide trap model based on tunneling of carriers from the semiconductor surface is unified with the two-band Shockley-Read-Hall type of capture and emission model for interface states. The new model explains the often observed upturn of MOS conductance at high frequencies when biased in inversion. The unified two-band model fully covers both types of charge traps in all MOS bias regions.

Systematic study of interfacial reactions induced by metal electrodes in high-k/InGaAs gate stacks

We systematically studied the effects of metal electrodes on high-k/InGaAs gate stacks and observed that the remote reactions—both oxidation and reduction—at the interface between the high-k dielectrics and InGaAs were thermodynamically initiated by the metal electrodes. Metal electrodes with negative Gibbs free energies (e.g., Pd) resulted in the oxidation of the InGaAs surface during the forming-gas annealing. In contrast, with TiN electrodes, which have a positive Gibbs free energy, the native III–V oxides underwent the reduction between the high-k dielectrics and InGaAs. We demonstrated that the reduction of native III–V oxides by metal electrodes improved the interface quality of the high-k/InGaAs gate stacks and produced an interface trap density (Dit) at the mid-gap with a value as low as 5.2 × 1011 cm−2 eV−1 with a scaled capacitance-equivalent thickness.

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

We present a review of our recent studies of BTI in FET devices fabricated in different material systems, highlighting the reliability opportunities and challenges of each device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge pMOS technologies when a Si cap is used to passivate the channel and to fabricate a standard SiCh/HfCh gate stack. We ascribe this superior reliability to a reduced interaction of channel holes with oxide defects, thanks to a favorable energy alignment of the (Si)Ge Fermi level to the dielectric stack We discuss gate stack optimization (Ge fraction, quantum well and Si cap thicknesses, channel strain engineering) for maximum BTI reliability, and we propose a simple model able to reproduce all the experimental trends. We then invoke the model to understand the excessive BTI in other high-mobility channel gate stacks, as Ge/GeOx/high-k and InGaAs/high-k Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability.

Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiOx interlayer between SiO2 and HfO2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices

In this paper, we present the results of a detailed study done on the correlation between frequency dispersion observed in AC admittance measurements and threshold voltage shifts observed in BTI reliability measurements on III-V MOS devices. We developed a detailed AC admittance model for MOS devices with border traps to study the effect of trap parameters on the AC admittance. We show, with the help of simulations and experiments, a clear correlation between border trap characteristics in AC admittance and BTI behavior. In addition, we propose a simplified and quick method to qualitatively characterize border traps using G/ω as a measure for their density.

BTI reliability of InGaAs nMOS gate-stack: On the impact of shallow and deep defect bands on the operating voltage range of III-V technology

In this work, we show that the reliability of InGaAs channel MOS devices not only depends on density of shallow defect states (i.e., electron traps responsible for PBTI in Si devices), but it is also governed by the density of deep defect states. This limits the operating range of the device. We conclude that it is necessary to characterize both shallow and deep defect densities in order to determine the total operating window (i.e., maximum underdrive and overdrive) of III-V devices for future technologies. We also show that a gate-stack comprising of a new ASM interface layer (ASM-IL), a LaSiOx interlayer and high-k dielectric can achieve the required reliability targets for a low power technology such as III-V.