Stefano Aresu

Automotive 130 nm smart-power-technology including embedded flash functionality

In this paper a 130 nm BCD technology platform is presented. The process offers logic-devices, flash-devices and high voltage devices with rated voltages up to 60 V. There are HV analog devices with variable channel length and HV power devices with low on-resistances. To ensure the safe operation of the power devices, a superior robustness against high energetic pulses of different length and repetitions could be achieved. The isolation of the different voltage stages is ensured by deep trenches and highly doped buried layers.

A Study of NBTI and Short-Term Threshold Hysteresis of Thin Nitrided and Thick Non-Nitrided Oxides

Negative bias temperature instability (NBTI) degradation and recovery have been investigated for 7-50-nm non-nitrided oxides and compared to thin 1.8- and 2.2-nm nitrided oxides from a dual work function technology. A wide regime of stress fields from 2.5 to 10 MV/cm has been covered. Thermal activation has been studied for temperatures from 25 degC to 200 degC. The NBTI effect for the nitrided oxide is larger than for non-nitrided oxides. The percentage of threshold shift V th which is ldquolostrdquo during a long measurement delay-which is the quantity leading to curved V th versus stress-time curves and to errors in extrapolated lifetimes-is about equal for nitrided or thick non-nitrided oxides. The fraction of recovered V th is strongly dependent on stress time but only weakly dependent on stress field. Recovery in thick oxides leads to exactly the same problems as for non-nitrided oxides, and clearly, a fast measurement method is needed. The effect of short-term threshold shifts has been studied for extremely short stress times down to 200 ns.

Physical understanding and modelling of new hot-carrier degradation effect on PLDMOS transistor

Hot carrier injection, inducing source-drain current (IDS) increase in p-channel LDMOS transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the on-resistance (RON) is observed [1, 5]. However, it has never been observed before, that the RON drift becomes constant after long stress time and the device resistance is not increased further afterwards. As soon as the RON almost reaches its constant level, the threshold voltage shift begins. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at room temperature is reported.

On the PBTI degradation of pMOSFETs and its impact on IC lifetime

Negative Bias Temperature Instability (NBTI) of pMOSFETs is nowadays the most prominent device degradation mechanism reported in the literature and a limiting factor for CMOS technology scaling. In contrast, for Positive Bias Temperature Instability (PBTI) of pMOSFET only very few publications can be found [1–4]. Most of the PBTI work is done for nMOSFETs from process nodes employing high-K dielectrics and not for pMOSFETs with silicon oxide dielectrics. Especially product related degradation based on application conditions leading to PBTI of pMOSFETs are not investigated satisfactorily. Furthermore an in-depth comparison of the impact on extrapolated product lifetime of NBTI, PBTI and the effect of NBTI & PBTI stress in sequence is missing.

Exceptional operative gate voltage induces negative bias temperature instability (NBTI) on n-type trench DMOS transistors

Abstract In some automotive applications, high negative bias is used to faster switch off n-type devices. This exceptional operative gate voltage at relative high temperature can induce instability of device parameters (e.g. threshold voltage, transconductance, saturation current, etc. In this work we will show that positive charge trapping generated under exceptional negative bias can induce large threshold voltage shift. Even if the effect can partially recover during the standard operative condition, nevertheless large Vth, shift are still present and can affect the correct functionality of the device.

Hot-carrier and recovery effect on p-channel lateral DMOS

Hot-carrier, inducing source-drain current (IDS) increase in high-voltage p-channel lateral DMOS (LDMOS) transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), electrons are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel towards the source side (Figure 1). The source drain current (Ids) increase leads to threshold voltage shift (Vth→0V) and for higher stress conditions a drain-source leakage can be observed. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at low temperature is reported.

Impact and measurement of short term threshold instabilities in MOSFETs of analog circuits

Short term threshold instabilities may cause erratic behavior in analog circuits like comparators and analog-to-digital-converters. As conventional characterization procedures have not been appropriately sensitized to such issues, this kind of erratic behavior usually only occurs in products where it is very difficult to identify. Therefore, for example prior to the introduction of a new gate stack, it is essential to do a careful experimental characterization of short term threshold instabilities, which goes beyond standard NBTI or PBTI measurements. A reliable forecast of the effect of threshold instabilities on the performance of analog circuits will require circuit simulations taking the threshold instabilities into account.

Analysis of ESD protection structure behaviour after ageing as new approach for system level reliability of automotive power devices

Abstract ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime. All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002]. The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress. The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.

Hot-carrier induced dielectric breakdown (HCIDB) challenges of a new high performance LDMOS generation

A new generation of embedded-power technologies offering high performance LDMOSFETs was introduced and particularly the reliability of the devices were characterized. The combination of a 120nm logic process with LDMOS with thin gate oxide enables high efficiency power converters on small die sizes. The reliability of the new LDMOS transistors had to be optimized very accurately to achieve both reliable products and the new RON benchmark.

New aspects for lifetime prediction of bipolar transistors in automotive power wafer technologies by using a power law fitting procedure

Abstract Bipolar transistors are part of the design manuals of almost all semiconductor wafer technologies. These design library devices must be qualified and released according to the present qualification standards, e.g. AEC (automotive electronic council) or JEDEC [Automotive Electronic Council. AEC-Q100-Rev-F; 2003; Automotive Electronic Council. AEC-Q101-Rev-C; 2005; JEDEC JP-001. Foundry process qualification guideline; 2002]. Dedicated stress tests (e.g. high temperature electrical operation (HTEO), bias temperature stress (BTS) or emitter base reverse bias (EBRB)) must be performed to check device specific drift and degradation mechanisms. A lifetime prediction must be performed on base of the determined device parameter drifts. The mentioned qualifications tests are arranged at typical device application conditions for electrical operation and temperature. Due to the breakdown behaviour of bipolar transistors the electrical operation parameters are limited to the save-operation-area (SOA). This excludes the possibility of any acceleration during these tests. Based on this fact the final check of the requested device lifetime in customer applications can be performed only by non-accelerated end-of-life tests. The paper shows a review of typical stress tests of dedicated bipolar transistors of an automotive power wafer technology. A presentation of the drift behaviour of the current gain (beta) parameter as function of stress time and qualification test is presented. In order to replace the end-of-life test requirement and to find a new approach to estimate the expected lifetime in the final device application a power law fitting procedure will be introduced. New aspects to discuss these results with respect to the defined lifetime target will be shown.