Lily Zhao

Flip Chip Package-in-Package (fcPiP): A New 3D Packaging Solution for Mobile Platforms

A new chip scale package is developed for use in high end cellular handsets and mobile products. The package houses a Baseband device, a pre-packaged Memory device and an Analog device in a 3-high stacked Package-in-Package (PiP) configuration wherein the base band die is attached to a 4-layer 1-2-1 Build-up laminate substrate using flip chip interconnection and the Memory package and Analog die are interconnected to each other as well as to the substrate using wire bonding. The package represents the ultimate in integration, wiring density, high performance and miniaturization. The development of the package was accomplished through close co-working of multidisciplinary teams comprising packaging, design and device architecture. The paper describes the challenges in the development of the individual packaging technologies such as bumped wafer thinning, thin die flip chip attach and underfilling, low loop wire bonding and the integration of those technologies, such as flip chip and wire bonding on the same substrate, underfill and overmolding, and chip-package interactions in the form of parametric shifts in sensitive analog circuitry on the die. The assembly process, reliability and failure modes observed are described in detail including the eventual qualification of the package and its introduction into volume production.

Challenges and opportunities of chip package interaction with fine pitch Cu pillar for 28nm

As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu and LK (Low-k dielectric) material have been introduced to reduce such delays and allow higher device speed and better performance. However, since dielectric material with low-k value usually possesses large amount of porosity, its mechanical properties are degraded significantly which leads to fragile silicon backend structure. This in turn brings in reliability issues like LK cracking due to CPI (Chip Package Interaction). The application of flip-chip packaging introduces significant amount of mechanical stress on BEOL (Back-End-Of-Line) at chip-attach processing step due to CTE mismatch, and makes CPI much more challenging and critical for silicon integration. At advanced technology nodes, increasing performance demand of mobile processors coupled with SoC integration is one major driver of bump pitch reduction [1]. Higher I/O count can be achieved with finer bump pitch since die size very likely stays constant if not shrinking further. Cu pillar and ELK material have been introduced in 28nm to realize the pitch reduction and performance gain. Small UBM structure is required with fine pitch Cu pillar which introduces large amount of stress in BEOL layers. On the other hand, while k-value of ELK is reduced by ~20% compared to LK used in previous technologies, its hardness and mechanical modulus have been reduced by ~30%, resulting in major reduction of ELK material strength. In this paper, we present our key learnings from 28nm CPI development with fine pitch Cu pillar. Empirical data based on CPI TV as well as mechanical stress simulations are discussed. UBM dimension which is a critical factor with Cu pillar from CPI perspective is searched at fine pitch, and our data shows CPI robustness limits pitch reduction with Cu pillar if using standard mass reflow process. ELK robustness is also tested at different process corners, including UBM size, bump height and Cu etching module. Some ELK marginality issues are discovered at certain process corner combinations. CPI margin at 28nm with fine pitch Cu pillar is then assessed by correlating mechanical stress simulation to thermal shock testing data. It is shown that min ~15% ELK margin in terms of max ELK stress is necessary to ensure no ELK delamination happening at process corners. Impact of IMC (Intermetallic Compound) and Ni barrier are also studied. It is found that growth of IMC is critical for ELK integrity with mass reflow process. Once IMC is fully grown between Cu pillar and substrate bonding pad, since its stiffness is 2~3X higher than Lead-free solder, mechanical stress on ELK layers increases dramatically. Additional work is carried out to minimize the growth of IMC. It is confirmed that addition of Ni barrier effectively suppresses IMC growth, and increases CPI margin at process corners by considerable amount. Detailed data is presented and final recommendations on fine pitch Cu pillar conclude the paper.

Chip Package Interaction with fine pitch Cu pillar bump using mass reflow and thermal compression bonding assembly process for 20nm/16nm and beyond

This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate bump cell structures are proposed.

Quantifying impact of design parameters on Ultra-Low k ILD reliability in fine pitch Cu bump interconnect structures

Increasing feature integration into mobile processors and high performance require denser IO as well as more power/ground pin count. Specifically DDR speed is one of the major drivers for more IO which is realized by aggressively reducing bump pitch. Cu interconnect as well as ULK (Ultra-Low k) dielectric is introduced for such fine pitch processors at advanced Silicon nodes, and the reliability of ULK dielectric is the key concern of CPI (Chip Package Interaction). Since the bump cell size has to be reduced at fine pitch, the thermal-mechanical stress in ULK due to packaging assembly process increases significantly. Robust CPI solutions that address ULK reliability have to be defined at each Si technology node with sufficient margin to cover process variations and provide design flexibility. In this paper, we summarize our findings about impacts of design parameters on ULK reliability. First, since the mechanical stress is approximately inversely proportional to unit bump cell size, experimental study is carried out with various bump cell size at process corner conditions. Bump cell with circular shaped UBM that meets both assembly and CPI requirements without adversely affecting the design space is successfully developed for fine pitch applications. Our data shows reducing bump cell size further will increase CPI risk significantly, and may not be suitable for certain package configurations. Second, bump cell with non-circular shaped UBM is investigated to meet even tighter fine pitch requirement. Data suggests it is critical to understand the ULK reliability impact of both bump cell size as well as orientation of UBM major axis due to its non-circular shape. It is found that, with proper design guidelines, non-circularshaped bump cell can greatly improve CPI margin compared to circular-shaped ones. Third, impact of bump density and die size are studied using thermal shock testing and numerical simulation. It is found that, at design stage, global as well as local UBM density near die corner and periphery area must be carefully considered to prevent any ULK delamination. Impact of die size due to DNP effect is also discussed. Numerical simulation is used in this paper to simulate mechanical stress in ULK dielectric material during packaging assembly process. It is necessary to include Si BEOL stackup, correct material properties and detailed Cu bump interconnect structures in the model for accuracy. However, due to the complexity and length-scale range of BEOL stackup, it is not possible to capture all the details in numerical models. Assumptions and simplifications must be made in the model on various geometry and material parameters including BEOL stackup. Metal, oxide as well aspassivation layer properties need to be smeared using composite material principles. Different material and metal/ILD layer homogenization techniques of BEOL are tested numerically in this work. A paper study comparing mechanical stress of two different BEOL stackup using those homogenization techniques is presented. Further, impact of BEOL metal layers on ULK reliability is studied using simulation, and overall trend is summarized.

The electromigration behavior of copper pillars for different current directions and pillar shapes

A significant asymmetry in electromigration behavior was observed for copper pillars depending on the electron current direction; the electromigration performance is very robust for an electron source at the die-side, but vulnerable to the opposite electron flow direction. Through extensive failure analysis, it was observed that die-side electron source leads to a stable layering of intermetallic compounds and no electromigration-induced voiding, while the substrate-side electron source leads to more extensive transformation into intermetallic compounds at the expense of the copper trace as well as electromigration-induced voiding. These phenomena were exacerbated by narrower trace widths but improved by an oblong pillar shape. Further, the presence of a nickel cap between the solder and pillar did not significantly impact electromigration lifetime.

The impact of 45 to 28nm node-scaling on the electromigration of flip-chip bumps

The impact of 45nm to 28nm node-scaling on the electromigration of lead-free flip-chip bumps has been studied. Specifically, different UBM and PI open sizes as well as plated Ni and sputtered Cu UBM thicknesses were experimentally investigated. UBM sizes between 84 and 65 μm directly impact lifetime, while PI open diameters between 30 to 20 μm did not. A current-density exponent (n) value of 1 was measured when Joule heating is neglected, thereby suggesting a void-growth-limited mechanism. This value increases to 2 or greater when Joule heating is included, showing that Joule heating can strongly impact Imax extrapolations. Also, a thin plated Ni layer (1.5μm) and a thin sputtered Cu layer (2kÅ) independently led to significant early fails due to improper barrier coverage (rather than the thickness of the layer), which enhanced intermetallic transformation and therefore electromigration failure.