Michael Wickert

Integrated Adjustable Phase Shifters

When examining a monthly bank account statement, it is not only the number below the bottom line that matters. Whether that number has a minus or plus in front of it is crucial. For many technical problems, the sign matters as well. In circuits, we can change the sign by means of phase shifters. Moreover, by using phase shifters, intermediate states between the signs (including complex values) can be set in circuits. Hence, phase shifters play an important role in electrical engineering. Unfortunately, this article does not give direct insights to change the sign of your bank statement. However, it aims to give a comprehensive overview of tunable phase shifters for radio frequency (RF) applications including cookbooklike design guidelines and performance comparisons. The focus of this article is put on phase shifters fully integrated in a chip.

Multiband mixed-signal vector modulator IC

This paper presents an active BiCMOS vector modulator based RF weighting circuit suitable for WLAN diversity transceivers. It features a LNA, a SPI and 8-bit DACs for vector control and internal references. When mounted on a PCB, it delivers a maximum gain of 12 dB at 5.6 GHz. It draws a current of 17 mA from a 3.3 V supply. The whole design is free of bulky inductors thus requiring an area of only 1.3 mm2.

2–6-GHz BiCMOS Polar-Based Vector Modulator for

This paper presents and analyzes an active vector modulator based on the polar coordinate system and composed of circulator-based phase shifters and a variable gain amplifier. The design provides full phase control range of 360 and gain control range of 36 dB for a wide frequency range of 2-6 GHz. Phase and gain can be controlled with total root mean square (rms) linearity errors of 6.3 and 0.15 dB and rms correlation errors between gain and phase of 0.6 and 1.1 dB, respectively. Therefore, the design is suitable for RF diversity receivers in the - and -bands. The integrated circuit includes all necessary peripheral circuits, such as a digital control block and internal references and covers 1.06 on a 0.25- BiCMOS technology.

S

This paper presents an integrated 802.11a compliant receiver integrated circuit (IC), which is capable of processing four antenna signals using RF multiple-input multiple-output (RF-MIMO) schemes. Following four low-noise amplifiers, the weighting is performed using Cartesian vector modulators, whose output signals are combined and down-converted. The baseband filters, variable gain amplifiers (VGAs), a quadrature voltage-controlled oscillator, and digital interfaces are integrated. Experimental results demonstrate the performance of the individual components, as well as the RF-MIMO capabilities of the whole chip. The IC achieves a receiver noise figure of 3.6 dB, a phase noise of -113 dBc/Hz at 1-MHz offset, and an equivalent Cartesian weighting precision of 6 × 6 bit. An RF input signal of up to -35.3 dBm (1-dB compression) can be processed, while the maximum RF path gain amounts to 28.6 dB. The baseband VGA provides further 9-61-dB gain in 64 steps.

- and

The exploitation of multiple-input multiple-output (MIMO) benefits in the radio frequency (RF) domain adds special restrictions to the mixer design. This paper proposes a passive mixer core, which can be employed for both conversion directions in wireless local area network (WLAN) transceiver integrated circuits (ICs). Because in highly integrated direct conversion receivers an unknown level of self-mixing can occur, a method for regulating the DC-offset and common mode of the differential outputs is incorporated. Fabricated in 0.25 μm CMOS the mixer core consumes only 0.056mm2 in area. The measurement results of this 4.15 to 6.2 GHz direct conversion mixer prove excellent linearity OIP3 of +4.9 dBV, high voltage conversion gain +0.8 dB at an LO power of 5 dBm and a low power consumption of 11 mW at 2.5 V.

C

In this work, a fully differential CMOS attenuator for C-band comprising matching and control linearization loops is presented. At 5.6 GHz, a total attenuation range of 3.8–29.4 dB was measured. The phase changes only by ±6 ° in an attenuation control range of 15 dB. The control amplifiers draw a total current of 0.54 mA from a single 2.5 V supply.

-Band Diversity Receivers

Abstract This paper presents the design and results of a four-antenna integrated receiver (RX) frontend in 0.25 µm SiGe BiCMOS. It performs antenna combining in the radio-frequency (RF) domain with IEEE 802.11a compliant signals. Therefore, the RF part of this integrated circuit (IC) includes four low noise amplifiers (LNAs), vector modulators (VMs) and a signal combiner. These circuits can weight the incoming C-band (5.6 GHz) signals in their I- and Q-components with an 8-bit resolution before superposition and downcoversion. The baseband (BB) part of the applied zero-IF architecture integrates an 8th order switched-capacitor (SC) filter for channel selection and variable gain amplifiers (VGAs) for automatic gain control (AGC). Together with digital control logic the power consumption amounts to 350 mW at an area requirement of 7.5 mm2.

802.11a Compliant Spatial Diversity Receiver IC in

This paper describes the concept, implementation, integration, and verification of an RF-MIMO wireless LAN system called MIMAX. A test setup for trying out the complete MIMAX modem in laptop form factor is presented. The purpose is to verify, debug, and improve all the components and entire system taking into account real-time operation parameters (traffic load, timing, error recovery, etc.). The correctness of the front-end specific MIMAX control functions like beamforming weights handling and setting has been verified. The compatibility with the standard SISO IEEE802.11a WLAN has also been proved.

{\hbox{0.25-}}\mu{\hbox {m}}

This paper analyses several passive signal combiner concepts suited for RF MIMO schemes. After reviewing the requirements and theory of RF combiners in mobile applications the Wilkinson combiner is presented in several differential topologies suitable for integration into analogue frontends. A de-embedded gain of −7.6 dB @5.5 GHz per path is measured for a 4-to-1 passive combiner integrated in 0.25 µm BiCMOS. By careful inductor design the required area could be reduced by more than 50% with similar or even better performance. A simple bond-wire combiner is shown for comparison.

BiCMOS

In this paper we present the results of several key circuit blocks such as amplifiers, mixers and an oscillator in a 90 nm SOI CMOS technology. The circuits were optimized for low noise. Leading-edge results such as 3.8 dB noise figure (NF) up to 40 GHz and more than 8 dB gain up to 60 GHz for a wideband amplifier, a low loss of only 4.8 dB for a drain pumped transconductance mixer at 35 GHz consuming zero DC power, a third order intercept point (IIP3) of 15 dBm for a resistive mixer, and a phase noise of - 90 dBc/Hz at 1 MHz offset for a 60 GHz VCO (voltage controlled oscillator) are presented.