Stefan Hauptmann

A Jitter-Optimized Differential 40-Gbit/s Transimpedance Amplifier in SiGe BiCMOS

This paper studies the jitter performance at the input of the transimpedance amplifier (TIA) in a communication system based on multimode optical fibers. A method is shown to analyze and effectively reduce data-dependent jitter by proper choice of the TIA input resistance and the use of multiple feedback techniques. A 40-Gbit/s TIA in 0.25-μm BiCMOS with fT of up to 180 GHz is presented to demonstrate the efficiency of the jitter analysis. It shows 6 kΩ (75.5 dBΩ) transimpedance gain, 37.6-GHz bandwidth, open eyes, and less than 0.6-ps root mean square jitter at 40 Gbit/s, as well as best-in-class power consumption and noise performance.

V-band variable gain amplifier applying efficient design methodology with scalable transmission lines

In this study, a 60 GHz variable gain low noise amplifier with more than 20 dB gain is presented. An efficient design methodology employing scalable transmission lines is applied, which can avoid iterative EM simulations and predict the circuit behaviour very accurately. Different transmission line modelling approaches are compared to each other, and a simple yet flexible model is eventually chosen. The circuit has been fabricated and measured on-wafer. The power consumption of only 7.3 mW is, to the knowledge of the authors, the lowest value reported for a V-band amplifier.

Modeling bond wires for millimeter wave RFIC design

This paper discusses how bond wires can be accurately modeled for circuits operating at several 10 GHz. To obtain exact results a more sophisticated model than the commonly-used inductor with around 0.8 nH/mm is required. An edge-based multiple conductor transmission line (mtline) model is presented, and it is demonstrated how its parameters can be extracted from EM simulations. A comparison of the mtline model with a lumped components model demonstrates the advantages of the mtline approach.

Design methodology and characterization of a SiGe BiCMOS power amplifier for 60 GHz wireless communications

This paper presents design methodology and characterization of a 60 GHz class-A power amplifier and reviews in detail its design procedure, which requires only DC and small-signal models of the active devices. Different basic amplifier topologies are compared in order to select the best suited for a given technology. The design method is applied to a 60 GHz cascode power amplifier in a 0.25 μm SiGe BiCMOS technology working with a 3.0 V supply. Measurements show a power added efficiency of 22 % and an output power of 14.7 dBm. The compact single-stage amplifier has been implemented on an overall chip area of 0.34 mm2.

Small signal analysis of quadrature LC oscillator operating at 59-62.5 GHz

In this study, a comprehensive small signal analysis method for quadrature oscillators based on cross-coupled LC-tuned oscillators and parallel coupling is proposed. The analysis is suitable for circuits operating up to millimetre wave frequencies since the key parasitics of all circuit elements such as core amplifiers, coupling amplifiers, buffers, inductors and varactors are considered. This allows for efficient circuit and device optimisations. The proposed method is based on the consequent parallelisation of all individual network elements into a simple overall equivalent RLC tank. The analysis is employed for CMOS but can also be adapted to other technologies. To verify the analysis, a circuit with oscillation frequency around 61 GHz was designed in 90 nm silicon on insulator (SOI) CMOS. Frequency control is enabled by adjusting the gain in the feedback amplifiers. Hence, no lossy varactors are necessary. At 50 terminations, a supply voltage of 1.5 V and a total supply current of less than 56 mA, a tuning range above 3 GHz, an output power per channel of 19 dBm 1.5 dB and a phase noise of better than 80 dBc/Hz at 2 MHz offset are measured.

Low noise radio frequency integrated circuits in 90 nm SOI CMOS up to 60 GHz

In this paper we present the results of several key circuit blocks such as amplifiers, mixers and an oscillator in a 90 nm SOI CMOS technology. The circuits were optimized for low noise. Leading-edge results such as 3.8 dB noise figure (NF) up to 40 GHz and more than 8 dB gain up to 60 GHz for a wideband amplifier, a low loss of only 4.8 dB for a drain pumped transconductance mixer at 35 GHz consuming zero DC power, a third order intercept point (IIP3) of 15 dBm for a resistive mixer, and a phase noise of - 90 dBc/Hz at 1 MHz offset for a 60 GHz VCO (voltage controlled oscillator) are presented.