Michal Blaho

Schottky-barrier normally off GaN/InAlN/AlN/GaN HEMT with selectively etched access region

A Schottky-barrier normally off InAlN-based high-electron-mobility transistor (HEMT) with selectively etched access regions, high off-state breakdown, and low gate leakage is presented. Metal-organic chemical vapor deposition-grown 1-nm InAlN/1-nm AlN barrier stack is capped with a 2-nm-thick undoped GaN creating a negative polarization charge at a GaN/InAlN heterojunction. Consequently, the gate effective barrier height is increased, and the gate leakage as well as the equilibrium carrier concentration in the channel is decreased. After removal of the GaN cap at access regions by using a highly selective dry process, the extrinsic channel becomes populated by carriers. Normally off HEMTs with 8-μm source-to-drain distance and 1.8-μm -long symmetrically placed gate showed a source drain current of about 140 mA/mm. The HEMT gate leakage at a drain voltage of 200 V and grounded gate is below 10-7 A/mm with a three-terminal device breakdown of 255 V. The passivated InAlN surface potential has been calculated to be 1.45 V; significant drain current increase is predicted for even lower potential.

Adjustment of threshold voltage in AlN/AlGaN/GaN high-electron mobility transistors by plasma oxidation and Al2O3 atomic layer deposition overgrowth

We discuss possibilities of adjustment of a threshold voltage VT in normally off GaN high-electron mobility transistors (HEMTs) without compromising a maximal drain current IDSmax. Techniques of a low power plasma or thermal oxidation of 2-nm thick AlN cap over 3-nm thick AlGaN barrier are developed and calibrated for a thorough oxidation of the cap with a minimal density of surface donors at the inherent oxide-semiconductor interface. It has been shown that while a thermal oxidation technique leads to the channel and/or interface degradation, low density of surface donors and scalability of VT with additionally overgrown Al2O3 may be obtained for plasma oxidized HEMTs. With 10-nm thick Al2O3 deposited at 100 °C by atomic-layer deposition, we obtained VT of 1.6 V and IDSmax of 0.48 A/mm at a gate voltage of VGS = 8 V. Density of surface donors was estimated to be about 1.2 × 1013 cm−2, leaving most of the negative polarization charge at the semiconductor surface uncompensated. Further reduction of surface...

Annealing, temperature, and bias-induced threshold voltage instabilities in integrated E/D-mode InAlN/GaN MOS HEMTs

Threshold voltage instabilities are examined in self-aligned E/D-mode n++ GaN/InAlN/GaN MOS HEMTs with a gate length of 2 μm and a source-drain spacing of 10 μm integrated in a logic invertor. The E-mode MOS HEMT technology is based on selective dry etching of the cap layer which is combined with Al2O3 grown by atomic-layer deposition at 380 K. In the D-mode MOS HEMT, the gate recessing is skipped. The nominal threshold voltage (VT) of E/D-mode MOS HEMTs was 0.6 and −3.4 V, respectively; the technology invariant maximal drain current was about 0.45 A/mm. Analysis after 580 K/15 min annealing step and at an elevated temperature up to 430 K reveals opposite device behavior depending on the HEMT operational mode. It was found that the annealing step decreases VT of the D-mode HEMT due to a reduced electron injection into the modified oxide. On the other hand, VT of the E-mode HEMT increases with reduced density of surface donors at the oxide/InAlN interface. Operation at the elevated temperature produces rev...

ZrO2/InAlN/GaN Metal?Oxide?Semiconductor Heterostructure Field-Effect Transistors with InAlN Barrier of Different Compositions

We report on InAlN/GaN heterostructure metal-oxide-semiconductor field-effect transistors (MOSHFETs) with an InAlN barrier layer of different compositions (x(InN) 13, 17, and 21%) and ZrO2 gate-insulator/passivation. Static measurements yielded higher drain currents than those on unpassivated HFET counterparts and the currents increased with decreased x(InN). Post deposition annealing of the ZrO2 insulator had less influence on the static performance but remarkable changes were observed on the capacitance-voltage characteristics. The capacitance hysteresis in both channel depletion and barrier accumulation regions was significantly suppressed after annealing. This indicates a reduction of the interfacial trap states and of fixed charge in the oxide. Pulsed current-voltage measurements confirmed this conclusion-the gate lag of only similar to 80% was evaluated for 200 ns pulse width, independently on the composition of the InAlN barrier layer. These results support an application of high permittivity ZrO2 gate-insulator/passivation for the preparation of high-performance InAlN/GaN MOSHFETs

Technology of integrated self-aligned E/D-mode n++GaN/InAlN/AlN/GaN MOS HEMTs for mixed-signal electronics

We describe the technology and performance of integrated enhancement/depletion (E/D)-mode n++GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate structure. An identical starting epi-structure was used for both types of devices without the additional need for a contacts regrowth. The n++GaN cap layer was etched away in the gate trenches of the E-mode HEMT while it was left intact for the D-mode HEMT. The plasma etching process was shown to be highly selective between the cap and the InAlN barrier and also to polish the InAlN surface. However, different GaN etching initiation times inside and outside the mesa region were obtained. Gate contacts were isolated using a dielectric layer deposited at low temperature through an e-beam resist to retain the self-aligned approach. Feasibility of the approach for future fast GaN-based mixed-signal electronic circuits was shown by obtaining alternative HEMT threshold voltage values of +0.8 V and −2.6 V, invariant maximal output current of ~0.35 A mm−1 despite large source-to-drain distances and by demonstrating a functional logic invertor.

Origin of positive fixed charge at insulator/AlGaN interfaces and its control by AlGaN composition

The key feature for the precise tuning of Vth in GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors is the control of the positive fixed charge (Qf) at the insulator/III-N interfaces, whose amount is often comparable to the negative surface polarization charge ( Q p o l −). In order to clarify the origin of Qf, we carried out a comprehensive capacitance-voltage (C-V) characterization of SiO2/AlxGa1–xN/GaN and SiN/AlxGa1–xN/GaN structures with Al composition (x) varying from 0.15 to 0.4. For both types of structures, we observed a significant Vth shift in C-V curves towards the positive gate voltage with increasing x. On the contrary, the Schottky gate structures exhibited Vth shift towards the more negative biases. From the numerical simulations of C-V curves using the Poissons equation supported by the analytical calculations of Vth, we showed that the Vth shift in the examined MIS structures is due to a significant decrease in the positive Qf with rising x. Finally, we exa...

Post-deposition annealing and thermal stability of integrated self-aligned E/D-mode n ++ GaN/InAlN/AlN/GaN MOS HEMTs

We describe technology and evaluate thermal performance of enhancement/depletion (E/D)-mode n++GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate processing, where n++GaN layer was etched away only under the gate for E-mode and for D-mode stay intact. Gate contacts were isolated using a dielectric layer deposited at low temperature through an e-beam resist to retain the self-aligned approach. Threshold voltage of the as deposited E- and D-mode HEMTs was +0.6 V and -2.4 V, respectively. After post-deposition annealing (PDA) at 300 °C in N2 atmosphere the threshold voltage has been changed to +3 V and - 4,4 V for E- and D-mode HEMTs, respectively. These effects were explained by decreasing density of deep interface states in the D-mode HEMTs and decreasing surface donors at the semiconductor-oxide interface in case of the E-mode HEMTs. After PDA, electrical performance of both types of transistors was evaluated from room temperature to 150 °C. At elevated temperatures, injection and trapping of electrons from the gate metal to the oxide was found in D-mode HEMTs, while emission of electrons from the oxide-semiconductor interface states was crucial for the E-mode ones.

Resistive switching in nonplanar HfO2-based structures with variable series resistance

The authors have prepared μm-sized HfO2-based nonplanar resistive switching cells with TiN and Pt electrodes. The structures exhibited stable resistive switching loops with low resistance state current below 1 mA. The influence of series resistance of the TiN strip electrode on the switching characteristics was measured and simulated. It was shown that the series resistance reduces the low state resistance current as well as high to low resistance state ratio.

Hafnium oxide and tantalum oxide based resistive switching structures for realization of minimum and maximum functions

While the main application of resistive switching structures currently targets non-volatile memories, increasing interest is being focused on their logic applications. Resistive switches are suitable for Boolean logic, neuromorphic computing and for implementation of Zadeh fuzzy logic. In this work, we analyzed implementation of the resistive switching structures for logic application based on Zadeh fuzzy logic. Resistive switching structures based on hafnium oxide and tantalum oxide were connected in an anti-serial configuration (complementary resistive switch). The complementary resistive switches integrated into logic circuit for Min-Max function implementation were analyzed using quasi-static voltage sweeps. We have shown that the accuracy of the Min/Max function determination depends on the ratio of the high and low resistivity states of the single switches. Determination of the Min/Max values is relevant only above the threshold voltage of the resistive structures. Reproducibility of the Min/Max function constructed from the resistive switching structures was evaluated. In addition, pulsed reconfiguration of complementary resistive switch using 100 ns long pulses was demonstrated.While the main application of resistive switching structures currently targets non-volatile memories, increasing interest is being focused on their logic applications. Resistive switches are suitable for Boolean logic, neuromorphic computing and for implementation of Zadeh fuzzy logic. In this work, we analyzed implementation of the resistive switching structures for logic application based on Zadeh fuzzy logic. Resistive switching structures based on hafnium oxide and tantalum oxide were connected in an anti-serial configuration (complementary resistive switch). The complementary resistive switches integrated into logic circuit for Min-Max function implementation were analyzed using quasi-static voltage sweeps. We have shown that the accuracy of the Min/Max function determination depends on the ratio of the high and low resistivity states of the single switches. Determination of the Min/Max values is relevant only above the threshold voltage of the resistive structures. Reproducibility of the Min/Max fun...

Performance analysis of monolithically integrated depletion-/enhancement-mode InAlN/GaN heterostructure HEMT transistors

The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines the lithographic masks required for the fabrication process, is presented as well. The proposed mask set was designed taking into account the design-for-manufacturing approach. Furthermore, we evaluated measured properties and performance of the fabricated transistors and circuits and recalibrate the transistor models according to the latest measurements.