Michal Lodzinski

Si/SiC bonded wafer: A route to carbon free SiO2 on SiC

This paper describes the thermal oxidation of Si/SiC heterojunction structures, produced using a layer-transfer process, as an alternative solution to fabricating SiC metal-oxide-semiconductor (MOS) devices with lower interface state densities (Dit). Physical characterization demonstrate that the transferred Si layer is relatively smooth, uniform, and essentially monocrystalline. The Si on SiC has been totally or partially thermally oxidized at 900–1150 °C. Dit for both partially and completely oxidized silicon layers on SiC were significantly lower than Dit values for MOS capacitors fabricated via conventional thermal oxidation of SiC. The quality of the SiO2, formed by oxidation of a wafer-bonded silicon layer reported here has the potential to realize a number of innovative heterojunction concepts and devices, including the fabrication of high quality and reliable SiO2 gate oxides.

Si/SiC heterojunctions fabricated by direct wafer bonding

The physical and electrical properties of Si/SiC heterojunctions formed by direct wafer bonding are presented. Atomic force microscopy (AFM) and imaging reveal an improved bonding quality when Si wafers are transferred to on-axis substrates as opposed to off-axis epitaxial layers. AFM analysis of the bonded wafer achieves a smoother surface when compared to molecular beam epitaxy-grown Si layers. A reduced roughness of only 5.8 nm was measured for bonded wafers. Current-voltage measurements were used to extract the rectifying characteristics of Si/SiC heterojunctions. These Si layers could lead to improved high quality and reliable SiO2 gate oxides

Silicon carbide Schottky diodes and MOSFETs: Solutions to performance problems

Silicon carbide has long been hailed as the successor to silicon in many power electronics applications. Its superior electrical and thermal properties have delivered devices that operate at higher voltages, higher temperatures and with lower on-resistances than silicon devices. However, SiC Schottky diodes are still the only devices commercially available today. Though SiC Schottkys are now being used with silicon IGBTs in dasiahybridpsila inverter modules, the real advantages will be seen when silicon switching devices can be replaced by SiC. This paper describes the current state of SiC diode and MOSFET technology, discussing possible solutions to making these devices commercially viable.

Ellipsometric and MEIS Studies of 4H-SiC/Si/SiO2 and 4H-SiC/SiO2 Interfaces for MOS Devices

The high density of interface states of thermally grown oxides on silicon carbide has prompted research into alternative oxidation methods and post oxidation anneals. One such alternative is oxidation of a deposited sacrificial silicon layer. A recent variation of this technique is a partial oxidation of the deposited Si layer, so that a thin Si layer remains between the SiO2 and SiC layers. If the SiO2/Si interface has lower interface state densities than the SiO2/SiC interface, the SiO2/Si/SiC hetero-structure could yield improved channel mobilities in MOS devices. Moreover, by correct optimization of the MOSFET device structure, breakdown can be designed to occur in the bulk SiC layer, thus maintaining a high blocking voltage. Post oxidation annealing in N2O is another technique often used to reduce interface state densities. However, little is known about the chemical and physical nature of these N2O oxidized dielectrics. Ellipsometric and Medium Energy Ion Scattering (MEIS) investigations of conventional SiO2/SiC interfaces compared with SiO2/Si/SiC hetero-junction structures and N2O oxidized samples are reported.

Investigation of Graphene Growth on 4H-SiC

This paper reports the investigation of epitaxial graphene growth on 4H-SiC substrates. Growth has been performed under ultra high vacuum (UHV) conditions at temperatures ranging from 1150 to 1250°C, and the formation of the graphene layer has been monitored using X-ray photoelectron spectroscopy (XPS). A gradient of 100°C in temperature was introduced across the sample in order to grow a wide range of thicknesses along the sample. Atomic force microscopy (AFM) of the surface shows that the epitaxial graphene layer follows the topography of the bulk material and introduces very little surface roughness. This paper also reports the electrical characterisation of the graphene layers.

Investigation of Si/4H-SiC hetero-junction growth and electrical properties

This paper describes the growth and characterisation of Si/SiC heterojunction structures. Heterojunction structures are of interest for low on-resistance diodes and as potential solutions to fabricating SiC MOS devices with lower interface state densities. The formation of the Si/SiC heterojunction using Chemical Vapour Deposition (CVD), Molecular Beam Epitaxy (MBE), Electron Beam Evaporation under UHV conditions (EBE-UHV) and Layer Transfer (LT) are reported. The physical nature of Si/SiC structures has been investigated using scanning electron microscopy (SEM). Results of electrical characterisation of the Si/SiC heterojunctions, are also reported. Finally, thermal oxidation of a Si / SiC heterojunction structures has been performed. The C(V) characteristics of the resulting oxides are compared to conventional thermal oxides on SiC.

Modification of Schottky interface by the inclusion of DNA interlayer to create metal / organic / inorganic structures

In this paper, we describe the fabrication and testing of the organic/inorganic Al/DNA/Si Schottky diodes. DNA interlayers are introduced into silicon structures and their electrical characteristics are modified as a result of the Schottky barrier manipulation. Processing of the silicon and DNA is described and the details of the used materials are presented. The novel process step, introduction of an etched well, is described which enables defined concentrations of the DNA to be introduced onto the silicon structure. Techniques are described for verification of the structure throughout the fabrication process. Electrical measurements are made on the fabricated structures having different concentrations of DNA. These are compared, together with the identical structures fabricated without DNA interlayers, to show a parametric variation related to the DNA concentrations. Finally, imaging techniques are used to observe the structure of DNA on the silicon surface.

Silicon-on-SiC, a novel semiconductor structure for power devices

A physical and electrical analysis of Si/SiC heterojunctions formed by layer transfer based on the smartcut® process is presented in this paper. AFM and SEM have revealed a high bonding quality when Si wafers are transferred to SiC on-axis wafers. XRD points to the fact that the layers are monocrystalline in nature. A surface AFM analysis of the bonded wafers demonstrated a smooth surface (rms = 5.8 nm) suitable for semiconductor device fabrication. Capacitors have been fabricated from the Si/SiC heterojunctions, which have been totally oxidised. Oxidised Si/SiC structures yielded a lower density of interface states than conventional thermal oxidation techniques.

Metal Contacts to Boron-Doped Diamond

This paper describes the fabrication of Ni and Ti contacts to single crystal, boron-doped diamond. The electrical performance of metal-diamond contacts has been investigated using current-voltage I(V) characterization of circular transmission line model (CTLM) test structures. X-ray photoelectron spectroscopy (XPS) analysis of Ti/diamond contacts has been performed and is correlated with CTLM results. Post deposition annealing of metal-diamond contacts has a dramatic influence on contact resistivity, with lower resistances observed after annealing at 900°C. Specific contact resistances as low as 9 x 10-5 Ω.cm2 have been obtained. The effect of doping (via epitaxial growth and boron implantation) on metal-diamond contacts is also reported.

Characterization of MOS interfaces on protected and un-protected 4H-SiC surfaces

In this paper, we present investigations performed on 4H-SiC surfaces annealed at high temperature in the presence of a protective carbon cap and compare these to samples fabricated by the same process, but without a protective layer. The high temperature treatment resulted in sample surfaces with various roughnesses. The annealed samples have been oxidised to fabricate MOS structures in order to investigate the effect of annealing on the physical properties SiO2/SiC interfaces. Structures have been characterized using C-V measurements. Results suggest that treatments to reduce surface roughness caused by annealing, prior to any oxidation, are effective in reducing the density of interface traps. The density of SiO2/SiC interface traps for samples treated prior to oxidation is lower than interface trap densities for annealed samples with no preoxidation roughness reduction treatment.