Michel Frechette

A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

A highly-integrated SiGe BiCMOS WCDMA transmitter IC

A highly-integrated SiGe BiCMOS WCDMA transmitter IC consists of VHF, UHF chains, and synthesizers. At 6 dBm output power, it consumes 79 mA at 2.7 V, with a 5% r.m.s. EVM and -42 dBc ACLR at 5 MHz offset. In-band and receive-band output noise are -128 and -135 Bm/Hz, respectively. Fully integrated PLLs use on-chip VCO tanks and require no off-chip loop filters.

Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter

We present a systematic approach for the design and analysis of a high-resolution RF-DAC. The RF-DAC is implemented in 65 nm CMOS as an integral part of a digital polar EDGE transmitter based on the Digital-RF-Processor (DRP™). It combines the functionality of a traditional baseband DAC and a mixer. This paper addresses the issue of a transistor mismatch, which has become a key design challenge at fine geometry process nodes. A method is presented to analyze the mismatch, quantify it and relate it to the system specifications. The presented techniques are used in a commercial GSM/EDGE SoC radio, in which the transmitters wideband noise (WBN) performance significantly exceeds the EDGE specifications with more than 6 dB margin at 20 MHz offset from the carrier frequency.

An RF variable gain amplifier with linear-in-dB gain steps and automatic power consumption optimization

This paper describes a novel power optimized RF amplifier with linear in dB gain steps. Using basic P-N junction diode in 45nm CMOS process the implemented VGA provides large dynamic range with accurate linear-in-dB gain steps. The gain steps of the VGA do not depend on process variation and has a predictable variation across temperature. The VGA also has an automatic power reduction mechanism which reduces power consumption at low VGA gain.