Abhijit Kumar Das

A 90nm CMOS single-chip GPS receiver with 5dBm out-of-band IIP3 2.0dB NF

A single-chip GPS receiver with a low-IF heterodyne RF front-end includes a LNA, image-reject IQ mixers, a passive poly-phase filter, and a fully integrated synthesizer. The IF-strip consists of a jammer-reject filter, a VGA, a /spl Delta//spl Sigma/ ADC, and a digital IF-filter. The receiver dissipates 60 mA at 1.4 V and achieves a NF of 2 dB and out-of-band IIP3 of 5 dBm.

A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply

This paper describes a power and area efficient pipeline ADC design. This ADC was designed in 65nm process without any special mask requirement and can work with supply voltage of 1.3V consuming 10mW providing 9.7 ENOB at 80MSPS while occupying less than 0.2 square millimeters.

A 4/sup th/-order 86dB CT /spl Delta//spl Sigma/ ADC with two amplifiers in 90nm CMOS

A fourth-order 1b CT /spl Delta//spl Sigma/ converter using a two-amplifier loop and a 267MHz sampling frequency is implemented in 90nm CMOS. A double-loop architecture couples passive poles with a reduced number of active blocks to improve area and power while achieving 86dB peak SNR over a 600kHz band.

An RF variable gain amplifier with linear-in-dB gain steps and automatic power consumption optimization

This paper describes a novel power optimized RF amplifier with linear in dB gain steps. Using basic P-N junction diode in 45nm CMOS process the implemented VGA provides large dynamic range with accurate linear-in-dB gain steps. The gain steps of the VGA do not depend on process variation and has a predictable variation across temperature. The VGA also has an automatic power reduction mechanism which reduces power consumption at low VGA gain.

High precision yet wide range on-chip oscillator with dual charge-discharge technique

This paper describes a high precision all digital on-chip oscillator. This architecture can achieve absolute precisions beyond 0.1% with only one trim. Once trimmed, the oscillator can produce any frequency within the programmable range with similar accuracy. If there are multiple oscillators on same die, trimming one oscillator will be sufficient to trim all the oscillators at multiple frequencies. The designed prototype achieved better than 0.17% accuracy at 112MHz while consuming 250uA. The area for the oscillator is just 0.02mm2.

Continuous time ΣΔ modulator, challenges & possibilities

Single-bit SDM is not very suitable for wide bandwidth and high dynamic range applications even though they are the perfect choice in deep submicron digital process. This paper describes few novel approaches which achieves close to multi-bit modulator performance without losing the advantage of the single-bit modulator.