Michiaki Nakayama

A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.

A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation

With continuous scaling of process technology, embedded DRAM technology becomes promising for high performance cache memory systems because of its potential of large memory capacity and high bandwidth. Although several papers reported, none of them has enough memory bandwidth or capacity for high-end computer applications. This 16 MB cache DRAM LSI chip with internal 35.8 GB/s memory bandwidth and 9.0 ns DRAM random access latency uses merged logic DRAM process technology that combines leading-edge DRAM devices equivalent to that of 256 Mb conventional DRAM with high-speed 0.2 /spl mu/m CMOS logic.

On-chip dual-ring-oscillator-based random-fluctuation-measurement method for detecting lowest voltage in adaptive voltage scaling systems

A fully digital 40-nm-CMOS-based sensor using dual-ring oscillators for detecting random device fluctuation was developed. The sensor detects threshold voltage fluctuation of a MOSFET with precision of 1 mV with ±10% accuracy by calculating the squared sum of the differences in frequencies of the two ring oscillators. This sensing method does not require reference signals and achieves a smaller layout area than that of a conventional analog sensor.