Yuji Yokoyama

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage.

A 6-ns 256-kbit BiCMOS TTL SRAM

A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<<ETX>>

A 6-ns 256-kb BiCMOS TTL SRAM

The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25 degrees C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a *8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm*10 mm. >

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%

A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.

Circuit technologies for a 12 ns 4 Mb TTL BiCMOS DRAM at 3.3 V operation

Circuit technologies are described for a 4-Mb transistor-transistor logic (TTL) BiCMOS DRAM with a 12-ns access time. Successful 3.3-V operation is reported. New circuit technologies, such as a dynamic pull-up input buffer, a common drain BiNMOS decoder, and a direct bootstrap and two-level precharge architecture of the TTL output buffer, make it possible to realize fast access DRAMs. Detailed circuit descriptions of the input buffer and decoder and output buffer are provided, together with a tabular design summary.<<ETX>>