Mitsugu Kusunoki

A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS

A 450 MHz 64 b RISC processor die contains 8.3 M logic-gate transistors and 20 M RAM transistors. 0.25 /spl mu/m CMOS with 0.2 /spl mu/m Lg, 4 nm tox, 1.8 V Vdd, and 7-layer metal technology is used. Multiple-threshold-voltage design with minimum standby current is introduced. Previously-reported application of this technique is to limited to static circuits. Here it is applied not only to static circuits, but also to clock-distribution drivers, register files and dynamic circuits in RAM macros. Precise clock-skew control, PLL jitter minimization, and optimized buffer insertion on long wires are carried out in accordance with the critical path analysis.

A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST

A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.