Wilhelm C. Fischer

A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection

A burst-mode laser driver for passive optical networks (ATM-PON/FSAN, N-PON, π-PON) uses mixed-signal design techniques in digital 0.5-μm CMOS. Power consumption is 15 mW, which is about an order of magnitude less than previous designs. The laser driver features automatic power control and laser end-of-life detection. These features are implemented with a novel peak comparator, which operates on a packet-by-packet basis.

Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Measurements of a 0.5 /spl mu/m CMOS testchip using several techniques have demonstrated a reduction in the generation of ground bounce. These techniques are: an automatic transistor sizing method that compensates for process, temperature, and supply voltage variations; a self-adjusting internal capacitive load that counteracts the increased switching rate of faster parts; and an integrated resistive element inserted directly into the power and ground leads that dampens the RLC oscillations. Comparison measurements between a conventional buffer and the new buffer have demonstrated that the amplitude and duration of the generated ground bounce has been reduced 2.5/spl times/ and 2/spl times/, respectively. A single external resistor is required to set a reference current.

150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection

Two 0.9 /spl mu/m CMOS chips serve for burst-mode clock and data recovery applications specific to passive optical network (PON) systems. In each case, a core, first order clock recovery circuit is realized by two gated ring oscillators, indirectly frequency-tuned by a phase-locked loop using a third replica oscillator and a local reference signal. Instantaneous phase locking is guaranteed by restarting the gated oscillators every time input data transitions occur. This method has been demonstrated to be precise enough to handle input data patterns containing hundreds of bits between transitions without errors. In addition, the circuit is small and dissipates low power. However, the recovered clock signal thus obtained inherits all jitter present in the input data signal. This shortcoming has been overcome in the present designs by two different methods. The results are the total elimination of jitter propagation and the generation of clean data and clock output signals. The first chip operates at 150 Mb/s. Since the data is demultiplexed into 8 channels, the local reference signal runs eight times slower than the transmission rate. This allows ample time for jitter-rejection processing. The second chip operates at 30 Mb/s without a demultiplexer. The jitter rejection is accomplished with an elastic store based on five 1 b registers.

An I/O CMOS buffer set for silicon multichip module's (MCM)

A set of I/O CMOS buffers for MCM is described. When simulation results of the MCM buffers are compared against conventional standard cell CMOS buffers, several advantages emerge. The results indicate that the new buffers dissipate 5 times less power, reduce propagation delay from chip core to another core from 3-6 nsec, and increase the frequency of operation by 2.5 times when compared to conventional CMOS buffers. Actual measurements between these buffers confirm these simulation results.<<ETX>>

Digital transistor sizing techniques applied to 100K ECL CMOS output buffers

Regulated current levels have been maintained with a control circuit that digitally adjusts the effective width of a 0.9-/spl mu/m CMOS output buffer to generate 100 K ECL levels operating up to 800 MHz. A pseudo-random bit error rate test of the buffer operating at 1.6 Gb/s indicated no errors Digital sizing reduces the variation of internal power dissipation over operating conditions from 250% to 10%.<<ETX>>

A 9 Gbit/s bandwidth multiplexer/demultiplexer CMOS chip

A 622-MHz 28:7 multiplexer/demultiplexer (MUX/DEMUX) 0.9- mu m CMOS chip has been fabricated and tested. All inputs/outputs (I/O) communicate using 100 K ECL logic levels and are single-ended. The chip is packaged in a metal QFP (quad flat pack) package and generates less than 80 mV of ground noise when all outputs switch simultaneously. The total power dissipation is 2.5 W. The device has controlled loop-back paths for system diagnostic purposes. Tests show that the chip operates at more than 740 MHz.<<ETX>>

LOW COST, LOW POWER DIGITAL OPTICAL RECEIVER MODULE FOR 50 Mb/s PASSIVE OPTICAL NETWORK

A low cost digital optical receiver module for passive optical networks was developed. In order to reduce the cost of the receiver module, ICs are packaged in low cost plastic packages and the receiver module is fabricated using conventional surface mount technology. The receiver module is capable of receiving burst and packet digital optical signals, and recovered data and recovered clock in CMOS logic level are available. The receiver module contains a connectorized InGaAs PIN photodiode, a burst/packet mode-compatible preamplifier IC in a 32-lead TQFP plastic package, a comparator IC in an 8-lead SOIC plastic package, a clock recovery IC in a 32-lead TQFP plastic package and other active and passive components. These components are mounted on a four-layer printed wiring board. The intrinsic minimum receivable optical signal power is around -42 dBm/Ave and the dynamic range is over 26 dB for BER 1 × 10-8 at a bit rate of up to 60 Mb/s. The total power consumption of this module is less than 200 mW.

Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs

Compared to conventional packaging, multichip modules have significantly reduced capacitive loading in their interconnections. The authors present experimental results showing the performance of I/O buffers specially designed to operate in this environment, evaluated in several different silicon-on-silicon test modules.<<ETX>>

Design Techniques for Non-Oversampled, Instantaneously Locked Clock and Data Recovery Circuits - An Overview

Traditional narrow-band clock recovery circuits such as those based on LC tanks, SAW filters or PLLs suffer from the fundamental limitation of locking (reaching steady-state operation) slowly compared to the input data rate. This is inconsequential in classical digital links where phase-coherent data flows continuously. However, if data arrives in asynchronous packets, as it does in modern communication systems such as PON’s (Passive Optical Networks), long locking [times cause significant penalties in the transmission efficiency. For burst-mode applications new clock recovery methods with greater acquisition agility are needed.